IEICE Technical Committee

[Date]2016-11-28
[Paper #]VLD2016-51,DC2016-45

Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process

Michitarou Yabuuchi(KIT), Azusa Oshima(KIT), Takuya Komawaki(KIT), Kazutoshi Kobayashi(KIT), Ryo Kishida(KIT), Jun Furuta(KIT), Pieter Weckx(KUL/IMEC), Ben Kaczer(IMEC), Takashi Matsumoto(Univ. of Tokyo), Hidetoshi Onodera(Kyoto Univ.),

[Date]2016-11-28
[Paper #]VLD2016-52,DC2016-46

Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations

Kodai Yamada(KIT), Haruki Maruoka(KIT), Shigehiro Umehara(KIT), Jun Furuta(KIT), Kazutoshi Kobayashi(KIT),

[Date]2016-11-28
[Paper #]VLD2016-49,DC2016-43

Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System

Shigehiro Umehara(KIT), Jun Furuta(KIT), Kazutoshi Kobayashi(KIT),

[Date]2016-11-28
[Paper #]VLD2016-50,DC2016-44

Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)

Shunsuke Kogure(Shibaura Institute of Tech), Kimiyoshi Usami(Shibaura Institute of Tech),

[Date]2016-11-28
[Paper #]VLD2016-47,DC2016-41

Variable Pipeline Ultra Low-power Coarse Grained Reconfigurable Accelelator

Naoki Ando(Keio Univ.), Koichiro Masuyama(Keio Univ.), Hayate Okuhara(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2016-11-28
[Paper #]RECONF2016-41

2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting

Tomoya Kimura(Ritsumeikan Univ.), Hiroyuki ochi(Ritsumeikan Univ.),

[Date]2016-11-28
[Paper #]VLD2016-46,DC2016-40

A Novel Merge Network for FPGA Sorting Accelerators

Makoto Saitoh(Tokyotech), Susumu Mashimo(Tokyotech), Thiem Van Chu(Tokyotech), Kenji Kise(Tokyotech),

[Date]2016-11-28
[Paper #]RECONF2016-42

A Design Method of Circuits to Generate Stochastic Numbers with the Minimum Inputs

Ritsuko Muguruma(Ritsmeikan Univ.), Shigeru Yamashita(Ritsmeikan Univ.),

[Date]2016-11-28
[Paper #]VLD2016-44,DC2016-38

Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA

Manri Terada(Univ. of Aizu), Hayato Mashiko(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu),

[Date]2016-11-28
[Paper #]VLD2016-48,DC2016-42

Hardware implementation of PLC Instructions by high level synthesis

Ishigaki Yoshiki(TUT), Tanaka Tasuku(TUT), Fujieda Naoki(TUT), Ichikawa Shuichi(TUT),

[Date]2016-11-28
[Paper #]RECONF2016-43

Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)

Yusuke Yoshida(Shibaura Institute of Tech.), Kimiyoshi Usami(Shibaura Institute of Tech.),

[Date]2016-11-29
[Paper #]VLD2016-53,DC2016-47

Preliminary experimental platform for FlexPower FPGA evaluation

Toshihiro Katashita(AIST), Masakazu Hioki(AIST), Yohei Hori(AIST), Hanpei Koike(AIST),

[Date]2016-11-29
[Paper #]RECONF2016-47

Measurement of Vth Variation due to STI Stress and Inverse Narrow Channel Effect at Ultra-Low Voltage in a Variability-Suppressed Process

Yasuhiro Ogasahara(AIST), Hanpei Koike(AIST),

[Date]2016-11-29
[Paper #]CPM2016-76,ICD2016-37,IE2016-71

[Keynote Address] The development of video coding technology and contribution to HD transition

Akira Nakagawa(Fujitsu Labs.),

[Date]2016-11-29
[Paper #]VLD2016-60,CPM2016-82,ICD2016-43,IE2016-77,CPSY2016-53,DC2016-54,RECONF2016-50

[Keynote Address] CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era

Masanao Yamaoka(Hitachi),

[Date]2016-11-29
[Paper #]VLD2016-59,CPM2016-81,ICD2016-42,IE2016-76,CPSY2016-52,DC2016-53,RECONF2016-49

Vivado HLSによる○×ゲーム探索再帰記述のハードウェア化

Yuuya Hiroe(Ritumeikan Univ.), Masashi Ono(Ritumeikan Univ.), Tomonori Izumi(Ritumeikan Univ.), Lin Meng(Ritumeikan Univ.),

[Date]2016-11-29
[Paper #]RECONF2016-44

[Keynote Address] Data mining techniques and applications

Makoto Onizuka(Osaka Univ.),

[Date]2016-11-29
[Paper #]