Engineering Sciences/NOLTA-Reliability(Date:2013/11/20)

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[Date]2013/11/20
[Paper #]
目次

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[Date]2013/11/20
[Paper #]
A High-Speed FFT for a Solar Radio Burst Observation On a Radio Telescope

Hiroki NAKAHARA,  Yohei CHISHIKI,  Kazumasa IWAI,  Hiroyuki NAKANISHI,  

[Date]2013/11/20
[Paper #]RECONF2013-39
An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD

Kensuke KUSHIYAMA,  Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2013/11/20
[Paper #]RECONF2013-40
Circuit design for 3D-stacking using TSV interconnects

Kenichi Osada,  Futoshi Furuta,  Kenichi Takeda,  

[Date]2013/11/20
[Paper #]VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators

Yasuhiro Take,  Noriyuki Miura,  Hiroki Ishikuro,  Tadahiro Kuroda,  

[Date]2013/11/20
[Paper #]VLD2013-74,CPM2013-118,ICD2013-95,CPSY2013-59,DC2013-40,RECONF2013-42
Cu Wiring Technology for 3D/2.5D Packaging

Motoaki TANI,  Yoshihiro NAKATA,  Tsuyoshi KANKI,  Tomoji NAKAMURA,  

[Date]2013/11/20
[Paper #]VLD2013-75,CPM2013-119,ICD2013-96,CPSY2013-60,DC2013-41,RECONF2013-43
Chip Thinning Technologies for Chip Stacking Packages

Shinya TAKYU,  Tetsuya KUROSAWA,  

[Date]2013/11/20
[Paper #]VLD2013-76,CPM2013-120,ICD2013-97,CPSY2013-61,DC2013-42,RECONF2013-44
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"

Osamu MORI,  

[Date]2013/11/20
[Paper #]VLD2013-86,CPM2013-121,ICD2013-98,CPSY2013-62,DC2013-52,RECONF2013-45
Soft-core microprocessor for small reconfigurable device

Yuichi WATANABE,  Taisuke YAMAMOTO,  Yuki YOSHIDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2013/11/20
[Paper #]RECONF2013-46
Mapping of Java bytecode to virtual CGRA with implementation in FPGA

Yuki OGAWA,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2013/11/20
[Paper #]RECONF2013-47
A trade-off between hardware resources and detection accuracy for FPGA implementation of separability filters

Jimpei HAMAMURA,  Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/11/20
[Paper #]RECONF2013-48
ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length

Hiroki NISHIYAMA,  Masato INAGI,  Shinobu NAGAYAMA,  Shin'ichi WAKABAYASHI,  

[Date]2013/11/20
[Paper #]RECONF2013-49
Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems

Yukihito ISHIDA,  Yuki ANDO,  Shinya HONDA,  Hiroaki TAKADA,  Masato EDAHIRO,  

[Date]2013/11/20
[Paper #]RECONF2013-50
Toward VLSI Reliability Enhancement by Reconfigurable Architecture

Takao ONOYE,  Masanori HASHIMOTO,  Yukio MITSUYAMA,  Dawood ALNAJJAR,  Hiroaki KONOURA,  

[Date]2013/11/20
[Paper #]VLD2013-87,CPM2013-122,ICD2013-99,CPSY2013-63,DC2013-53,RECONF2013-51
Real Chip Evaluation of a low power reconfigurable accelerator with SOTB Technology

Hongliang SU,  Hideharu AMANO,  

[Date]2013/11/20
[Paper #]RECONF2013-52
Evaluation of The First Flex Power FPGA chip with SOTB transistors

Chao MA,  Masakazu HIOKI,  Takashi KAWANAMI,  Yasuhiro OGASAHARA,  Tadashi NAKAGAWA,  Toshihiro SEKIGAWA,  Toshiyuki TSUTSUMI,  Hanpei KOIKE,  

[Date]2013/11/20
[Paper #]RECONF2013-53
Dependability-increasing demonstration of an optically differential reconfigurable gate array

Masato SEO,  Minoru WATANABE,  

[Date]2013/11/20
[Paper #]RECONF2013-54
Architecture Evaluation Using the Place-and-Route Tool of a Reconfigurable Device MPLD

Tomoya YAMASHITA,  Masato INAGI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Takashi ISHIGURO,  

[Date]2013/11/20
[Paper #]RECONF2013-55
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[Date]2013/11/20
[Paper #]
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