Engineering Sciences/NOLTA-Reliability(Date:2013/09/11)

Presentation
表紙

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[Date]2013/9/11
[Paper #]
目次

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[Date]2013/9/11
[Paper #]
Study on Processor Architecture for Image Recognition

Masayuki MIYAMA,  

[Date]2013/9/11
[Paper #]RECONF2013-20
An Implementation of High Performance Stream Processing on a Reconfigurable Hardware

Eric-shun FUKUOKA,  Hideyuki KAWASHIMA,  Hiroaki INOUE,  Taro FUJII,  Koichiro FURUTA,  Tetsuya ASAI,  Masato MOTOMURA,  

[Date]2013/9/11
[Paper #]RECONF2013-21
Design and Evaluation of Stream Processor for Incompressive Fluid Computation based on Fractional-Step Method

Ryotaro CHIBA,  Hayato SUZUKI,  Ryo ITO,  Kentaro SANO,  Satoru YAMAMOTO,  

[Date]2013/9/11
[Paper #]RECONF2013-22
A Power-Performance model for 3-D stencil computation on an FPGA accelerator

Keisuke DOHI,  Kota FUKUMOTO,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/9/11
[Paper #]RECONF2013-23
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors

Takeshi HIRAO,  Dahoo KIM,  ITARU Hida,  Tetsuya ASAI,  Masato MOTOMURA,  

[Date]2013/9/11
[Paper #]RECONF2013-24
Nonvolatile reconfigurable device development platform using a phase change material

Takumi MICHIDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Kenichi SHIMOMAI,  Takashi ISHIGURO,  

[Date]2013/9/11
[Paper #]RECONF2013-25
A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique

Hongliang SU,  Weihan WANG,  Hideharu AMANO,  

[Date]2013/9/11
[Paper #]RECONF2013-26
A LUT Architecture Based on Partial Function of Shannon Expansion

Kyosei YANAGIDA,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2013/9/11
[Paper #]RECONF2013-27
Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD

Yuki YOSHIDA,  Takumi MICHIDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Kenichi SHIMOMAI,  Takashi ISHIGURO,  

[Date]2013/9/11
[Paper #]RECONF2013-28
Hardware Acceleration of Inverted Pendulum Control Processing by Using the High Level Synthesis Tool JavaRock

Daichi UETAKE,  Takeshi OHKAWA,  Takefumi MIYOSHI,  Takashi YOKOTA,  Kanemitsu OOTSU,  

[Date]2013/9/11
[Paper #]RECONF2013-29
Design method for hw/sw Complex System Guide to the Technical Report and Template

Yuichi OGISHIMA,  Masatoshi SEKINE,  

[Date]2013/9/11
[Paper #]RECONF2013-30
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems

Koichi ARAKI,  Yukinori SATO,  Yasushi INOGUCHI,  

[Date]2013/9/11
[Paper #]RECONF2013-31
The Circuit Configuration method of 3D FPGA-Array System "Vocalise"

Hiromasa KUBO,  Jiang LI,  Yusuke ATSUMARI,  Baku OGASAWARA,  Masatoshi SEKINE,  

[Date]2013/9/11
[Paper #]RECONF2013-32
A study of pipeline execution on PEACH2

Takaaki MIYAJIMA,  Takuya KUHARA,  Toshihiro HANAWA,  David THOMAS,  Hideharu AMANO,  

[Date]2013/9/11
[Paper #]RECONF2013-33
A Packet Classifier using Parallel EVMDD (k) Machine

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2013/9/11
[Paper #]RECONF2013-34
Development of Memory Management Framework for FPGA-based Prototyping

Shinya TAKAMAEDA-YAMAZAKI,  Kenji KISE,  

[Date]2013/9/11
[Paper #]RECONF2013-35
Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration

Tomoaki UKEZONO,  Koichi ARAKI,  

[Date]2013/9/11
[Paper #]RECONF2013-36
Color configuration method for an optically reconfigurable gate array

Takumi FUJIMORI,  Minoru WATANABE,  

[Date]2013/9/11
[Paper #]RECONF2013-37
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