Engineering Sciences/NOLTA-Reliability(Date:2013/05/13)

Presentation
表紙

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[Date]2013/5/13
[Paper #]
目次

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[Date]2013/5/13
[Paper #]
Challenging Connect6 Hardware Design Competitions

Kentaro SANO,  

[Date]2013/5/13
[Paper #]RECONF2013-1
An FPGA Implementation of the Progressive Tree Neighborhood Algorithm : Phylogenetic Tree Reconstruction with Maximum Parsimony

Henry Block,  Tsutomu Maruyama,  

[Date]2013/5/13
[Paper #]RECONF2013-2
Implementation and Evaluation of Data Compression Hardware for Bandwidth Enhancement of Multiple Data Streams

Tomohiro Ueno,  Yoshiaki Kono,  Kentaro Sano,  Satoru Yamamoto,  

[Date]2013/5/13
[Paper #]RECONF2013-3
FPGA Acceleration of Short Read Mapping

Yoko SOGABE,  Tsutomu MARUYAMA,  

[Date]2013/5/13
[Paper #]RECONF2013-4
Speed-up of Dynamically Reconfigurable Processor Array

Toru KATAGIRI,  Hideharu AMANO,  

[Date]2013/5/13
[Paper #]RECONF2013-5
Proposal of a Dependable Fine-grained Reconfigurable Device with ECC Technology

Yuki YOSHIDA,  Kentaro TAKAKI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Kenichi SHIMOMAI,  Takashi ISHIGURO,  

[Date]2013/5/13
[Paper #]RECONF2013-6
An optically reconfigurable gate array using a temperature dependable holographic memory

Retsu MORIWAKI,  Minoru WATANABE,  Akifumi OGIWARA,  

[Date]2013/5/13
[Paper #]RECONF2013-7
Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis

Hiroaki KONOURA,  Dawood ALNAJJAR,  Yukio MITSUYAMA,  Hiroyuki OCHI,  Takashi IMAGAWA,  Shinichi NODA,  Kazutoshi WAKABAYASHI,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2013/5/13
[Paper #]RECONF2013-8
A Challenge of Acceleration of DA Algorithm by Parallel Processing

Michiaki Muraoka,  

[Date]2013/5/13
[Paper #]RECONF2013-9
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication

Takashige UDA,  Morihiro KUGA,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2013/5/13
[Paper #]RECONF2013-10
Implementation of Speculative Gather System for CMA

Rie UNO,  Nobuaki OZAKI,  Mai IZAWA,  Akihito TSUSAKA,  Takaaki MIYAJIMA,  Hideharu AMANO,  

[Date]2013/5/13
[Paper #]RECONF2013-11
Performance model evaluation for 3-D stencil computation using a high-level synthesis tool

Keisuke DOHI,  Yoshihiro NAKAMURA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/5/13
[Paper #]RECONF2013-12
A defect-robust FPGA-IP core architecture

Motoki AMAGASAKI,  Kazuki INOUE,  Qian ZHAO,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2013/5/13
[Paper #]RECONF2013-13
Video based real-time feature extraction and abnormal action detection on an FPGA

Kaoru HAMASAKI,  Keisuke DOHI,  Yuuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/5/13
[Paper #]RECONF2013-14
FAST COMPUTATION OF THE OPTICAL FLOW USING FPGA

Yu TANABE,  Tsutomu MARUYAMA,  

[Date]2013/5/13
[Paper #]RECONF2013-15
An FPGA-based Sound Synthesizer and its GUI

Suguru OCHIAI,  Yoshiki YAMAGUCHI,  Yuetsu KODAMA,  

[Date]2013/5/13
[Paper #]RECONF2013-16
Performance Evaluation of Physical Unclonable Functions on Kintex-7 FPGA

Yohei HORI,  Toshihiro KATASHITA,  Kazukuni KOBARA,  

[Date]2013/5/13
[Paper #]RECONF2013-17
Study of Runtime Binary Acceleration on TCA node

Takaaki MIYAJIMA,  Takuya KUHARA,  Toshihiro HANAWA,  David THOMAS,  Hideharu AMANO,  

[Date]2013/5/13
[Paper #]RECONF2013-18
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