Engineering Sciences/NOLTA-Reliability(Date:2012/01/18)

Presentation
表紙

,  

[Date]2012/1/18
[Paper #]
目次

,  

[Date]2012/1/18
[Paper #]
Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications

Kotoko FUJITA,  Nadav BERGSTEIN,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-91,CPSY2011-54,RECONF2011-50
Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register

Keita MANABE,  Rika UEGAKI,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-92,CPSY2011-55,RECONF2011-51
Sound preprocessing circuit by consonant and vowel recognition system

Keita OKAMOTO,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-93,CPSY2011-56,RECONF2011-52
Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift

Takatoshi UCHIZONO,  Kazuya OSAKU,  Akinobu TSUYUKI,  Zhu LI,  Yoichi TOMIOKA,  Hitoshi KITAZAWA,  

[Date]2012/1/18
[Paper #]VLD2011-94,CPSY2011-57,RECONF2011-53
An Image Recognition System with Hierarchical Feature Learning Function

Masahiro ARIIZUMI,  Baku OGASAWARA,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-95,CPSY2011-58,RECONF2011-54
On a Decomposed MTMDDs for CF Machine

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2012/1/18
[Paper #]VLD2011-96,CPSY2011-59,RECONF2011-55
An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor

Kensuke KANEDA,  Kohei MATSUMOTO,  Nobuyuki YAMASAKI,  

[Date]2012/1/18
[Paper #]VLD2011-97,CPSY2011-60,RECONF2011-56
Extension of ITRON Specification OS for Multithreaded Processors

Rikuhei UEDA,  Kei FUJII,  Hiroyuki CHISHIRO,  Hiroki MATSUTANI,  Nobuyuki YAMASAKI,  

[Date]2012/1/18
[Paper #]VLD2011-98,CPSY2011-61,RECONF2011-57
Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router

Takeo NAKAMURA,  Hiroki MATSUTANI,  Michihiro KOIBUCHI,  Kimiyoshi USAMI,  Hideharu AMANO,  

[Date]2012/1/18
[Paper #]VLD2011-99,CPSY2011-62,RECONF2011-58
A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique

Moritoshi YASUNAGA,  Hiroki SHIMADA,  Shohei AKITA,  Takuya ADACHI,  Hidetoshi ISHIJIMA,  Yusuke KURIBARA,  

[Date]2012/1/18
[Paper #]VLD2011-100,CPSY2011-63,RECONF2011-59
A Bandwidth Control Scheme based on a Traffic Analysis for an on-Chip Router

Daiki YAMAZAKI,  Hiroki MATSUTANI,  Nobuyuki YAMASAKI,  

[Date]2012/1/18
[Paper #]VLD2011-101,CPSY2011-64,RECONF2011-60
A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP

Akiko HIRAO,  Hidetoshi TAKESHITA,  Haruka YONEZU,  Satoru OKAMOTO,  Naoaki YAMANAKA,  

[Date]2012/1/18
[Paper #]VLD2011-102,CPSY2011-65,RECONF2011-61
Architecture and Estimation of Reconfigurable Processor for Multimedia Processing

Asuka Hayashi,  Shuu'ichirou YAMAMOTO,  Hideo MAEJIMA,  

[Date]2012/1/18
[Paper #]VLD2011-103,CPSY2011-66,RECONF2011-62
Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit

Yusaku YAMAZAKI,  Takuya SUZUKI,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-104,CPSY2011-67,RECONF2011-63
A Mobile Robot System using Intelligent Circuit in Silicon

Takuya SUZUKI,  Yusaku YAMAZAKI,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-105,CPSY2011-68,RECONF2011-64
Merge of Functions in High-Level Synthesis Using Assembly Codes as Intermediate Representation

Fumiaki TAKASHIMA,  Nagisa ISHIURA,  Makoto ORINO,  Hiroyuki TOMIYAMA,  Hiroyuki KANBARA,  

[Date]2012/1/18
[Paper #]VLD2011-106,CPSY2011-69,RECONF2011-65
High-Level Synthesis of Hardware Relinkable to Software

Makoto ORINO,  Nagisa ISHIURA,  Hiroyuki TOMIYAMA,  Fumiaki TAKASHIMA,  Hiroyuki KANBARA,  

[Date]2012/1/18
[Paper #]VLD2011-107,CPSY2011-70,RECONF2011-66
The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams

Daiki KANOU,  Ryota YAMAZAKI,  Naohiko SHIMIZU,  

[Date]2012/1/18
[Paper #]VLD2011-108,CPSY2011-71,RECONF2011-67
12>> 1-20hit(35hit)