Engineering Sciences/NOLTA-Reliability(Date:2011/05/05)

Presentation
表紙

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[Date]2011/5/5
[Paper #]
目次

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[Date]2011/5/5
[Paper #]
Resource Sharing in FPGA and Implementation of Face-Angle Detection Algorithm using Impulse C

Takaaki MIYAJIMA,  Masatoshi ARAI,  Hideharu AMANO,  

[Date]2011/5/5
[Paper #]RECONF2011-1
Pattern Compression of FAST Corner Detection and its FPGA Implementation

Keisuke DOHI,  Yuji YORITA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2011/5/5
[Paper #]RECONF2011-2
An Implementation of Mean Shift Filter on FPGA

DangBaKhac TRIEU,  Tsutomu MARUYAMA,  

[Date]2011/5/5
[Paper #]RECONF2011-3
A real-time stereo vision system using a tree-structured dynamic programming on FPGA

Minxi JIN,  Tsutomu MARUYAMA,  

[Date]2011/5/5
[Paper #]RECONF2011-4
Context Synchronization Method for Reliable Softcore Processor System

Makoto FUJINO,  Noritaka KAI,  Yoshihiro ICHINOMIYA,  Motoki AMAGASAKI,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2011/5/5
[Paper #]RECONF2011-5
Evaluation of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures

Hiroaki KONOURA,  Yukio MITSUYAMA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2011/5/5
[Paper #]RECONF2011-6
Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation

Tadashi OKABE,  

[Date]2011/5/5
[Paper #]RECONF2011-7
Design and Implementation of a Portable Framework for PCI Express Interface

Shoichi IGARASHI,  Ryuhei MORITA,  Yuichi OKUYAMA,  Tsuyoshi HAMADA,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2011/5/5
[Paper #]RECONF2011-8
Development of Wireless Video Transmission Equipment in 5GHz MIMO-OFDM Using FPGA

Jun TAKIZAWA,  Takaya KAJI,  Shingo YOSHIZAWA,  Takashi GUNJI,  Morio TAWARAYAMA,  Yoshikazu MIYANAGA,  

[Date]2011/5/5
[Paper #]RECONF2011-9
A Virus Scanning Engine Using a 4IGU Emulator and an MPU

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2011/5/5
[Paper #]RECONF2011-10
ERATO MINATO Discrete Structure Manipulation System Project and Current Work on System Design Area

Shin-ichi MINATO,  

[Date]2011/5/5
[Paper #]RECONF2011-11
Acceleration of Smith-Waterman Algorithm on FPGAs

Akira FUKUI,  Masahiro FUJITA,  

[Date]2011/5/5
[Paper #]RECONF2011-12
FaSTARにおける流束の面積分計算高速化のためのOut-Of-Order機構(科学技術計算)

Takayuki AKAMINE,  Kenta INAKAGATA,  Yasunori OSANA,  Naoyuki FUJITA,  Hideharu AMANO,  

[Date]2011/5/5
[Paper #]RECONF2011-13
Evaluation of Scalable Streaming Array for High-Performance Stencil Computation with Low Memory Bandwidth

Kentaro SANO,  Yoshiaki HATSUDA,  Yoshiaki KONO,  Satoru YAMAMOTO,  

[Date]2011/5/5
[Paper #]RECONF2011-14
Optimization of Application Programs of SLD-1 : A Low Power Accelarator

Nobuaki OZAKI,  Yoshihiro YASUDA,  Yoshiki SAITOU,  Daisuke IKEBUCHI,  Masayuki KIMURA,  Hideharu AMANO,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  Mitaro NAMIKI,  Masaaki KONDO,  

[Date]2011/5/5
[Paper #]RECONF2011-15
Implementation and Evaluation of a low power accelerator SLD-2

Mai IZAWA,  Nobuaki OZAKI,  Yoshihiro YASUDA,  Masayuki KIMURA,  Hideharu AMANO,  

[Date]2011/5/5
[Paper #]RECONF2011-16
Power Consumption Evaluation of a Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA

Yohei HORI,  Toshihiro KATASHITA,  Akashi SATOH,  

[Date]2011/5/5
[Paper #]RECONF2011-17
An Implementation of Programmable Re-Ordering Unit for Array Processor

Tomoyoshi KOBORI,  Nozomi ISHIHARA,  Katsutoshi SEKI,  Masao IKEKAWA,  

[Date]2011/5/5
[Paper #]RECONF2011-18
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