IEICE Technical Committee

Engineering Sciences/NOLTA-Reliability(Date:2010/09/09)

Presentation

表紙

[Date]2010/9/9
[Paper #]

Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration

Hiroyuki KAWAI, Moritoshi YASUNAGA,

[Date]2010/9/9
[Paper #]RECONF2010-18

Real-time detection of line segments on FPGA

Jianyun ZHU, Tsutomu MARUYAMA,

[Date]2010/9/9
[Paper #]RECONF2010-19

A Regular Expression Matching Circuit Based on an NFA with Multi-Character Consuming

Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA,

[Date]2010/9/9
[Paper #]RECONF2010-20

Finite Field Arithmetic on a Reconfigurable Processor with Variable Word Size

Yuichiro SHIBATA, Ryuichi HARASAWA, Kiyoshi OGURI,

[Date]2010/9/9
[Paper #]RECONF2010-21

A Consideration of Reconfigurable Processor for accelerating RSA Cryptography

Takatoshi TAMAOKI, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2010/9/9
[Paper #]RECONF2010-22

Accelerating HMMER search using FPGA Grid

Toyokazu TAKAGI, Tutomu MARUYAMA,

[Date]2010/9/9
[Paper #]RECONF2010-23

Hardware Lossless-Compressors of Floating-Point Data Streams to Enhance Memory Bandwidth

Kentaro SANO, Kazuya KATAHIRA, Satoru YAMAMOTO,

[Date]2010/9/9
[Paper #]RECONF2010-24

Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications

Yuki YOSHIOKA, Tomoyuki KAWAMOTO, Taiga BAN, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2010/9/9
[Paper #]RECONF2010-25

An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs

Masatoshi NAKAMURA, Masato INAGI, Kazuya TANIGAWA, Tetsuo HIRONAKA, Masayuki SATO, Takashi ISHIGURO,

[Date]2010/9/9
[Paper #]RECONF2010-26

Design and Implementation of a GUI Tool for Circuit Design on MPLDs

Ken TAOMOTO, Hideyuki KAWABATA, Masato INAGI, Kazuya TANIGAWA, Tetsu HIRONAKA, Masayuki SATO, Takashi ISHIGURO, Toshiaki KITAMURA,

[Date]2010/9/9
[Paper #]RECONF2010-27

A Peformance Estimation Method for Dynamically Reconfigurable Architecture in Stream Processing

Fumihiko HYUGA, Takashi YOSHIKAWA,

[Date]2010/9/9
[Paper #]RECONF2010-28

Applications of optically reconfigurable gate arrays

Minoru WATANABE,

[Date]2010/9/9
[Paper #]RECONF2010-29

A MEMS addressing technique in optically reconfigurable gate arrays

Hironobu MORITA, Minoru WATANABE,

[Date]2010/9/9
[Paper #]RECONF2010-30

COGRE : A Novel Compact Logic Cell Architecture for Area Reduction

Yasuhiro OKAMOTO, Yoshihiro ICHINOMIYA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2010/9/9
[Paper #]RECONF2010-31

An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device

Qian ZHAO, Yoshihiro ICHINOMIYA, Yasuhiro OKAMOTO, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2010/9/9
[Paper #]RECONF2010-32

Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture

Shota ISHIHARA, Ryoto TSUCHIYA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA,

[Date]2010/9/9
[Paper #]RECONF2010-33

Removing context memory from Multi-Context Dynamically Reconfigurable Processors

Hideharu AMANO, Masayuki KIMURA, Nobuaki OZAKI,

[Date]2010/9/9
[Paper #]RECONF2010-34

Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration

Masayuki KIMURA, Kazuei HIRONAKA, Hideharu AMANO,

[Date]2010/9/9
[Paper #]RECONF2010-35