Engineering Sciences/NOLTA-Reliability(Date:2010/05/06)

Presentation
表紙

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[Date]2010/5/6
[Paper #]
目次

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[Date]2010/5/6
[Paper #]
FPGA Implementation of Fast Proportional Digital PID Control for DC-DC Converters

Kazuma HAMAWAKI,  Yuki MAEDA,  Masato SOEJIMA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  Fujio KUROKAWA,  

[Date]2010/5/6
[Paper #]RECONF2010-1
An FPGA implementation of Full-search variable block size motion Estimation

Shuichi ASANO,  ZhiShun ZHENG,  Tsutomu MARUYAMA,  

[Date]2010/5/6
[Paper #]RECONF2010-2
Real-time processing of contrast limited adaptive histogram equalization on FPGA

Kentaro KOKUFUTA,  Tsutomu MARUYAMA,  

[Date]2010/5/6
[Paper #]RECONF2010-3
A study on multicore designed MuCCRA-3: dynamically reconfigurable processor array

Eiichi SASAKI,  Yoshiki SAITO,  Masayuki KIMURA,  Hideharu AMANO,  

[Date]2010/5/6
[Paper #]RECONF2010-4
First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells

Masahiro KOGA,  Masahiro IIDA,  Motoki AMAGASAKI,  Yoshinobu ICHIDA,  Mitsuro SAJI,  Jun IIDA,  Toshinori SUEYOSHI,  

[Date]2010/5/6
[Paper #]RECONF2010-5
Digit-Serial Floating Point Unit for High Precision Scientific Computation Engine

Kazuya TANIGAWA,  Taiga BAN,  Tetsuo HIRONAKA,  

[Date]2010/5/6
[Paper #]RECONF2010-6
A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs

Tsuyoshi KIMURA,  Noritaka KAI,  Yoshiaki TSUTSUMI,  Motoki AMAGASAKI,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2010/5/6
[Paper #]RECONF2010-7
A datapath classification method for efficient arithmetic pipeline combining on FPGAs

Yui OGAWA,  Tomonori OOYA,  Yasunori OSANA,  Masato YOSHIMI,  Yuri NISHIKAWA,  Akira FUNAHASHI,  Noriko HIROI,  Hideharu AMANO,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2010/5/6
[Paper #]RECONF2010-8
Stream Processing brings out Performance of Wired Logic

Kiyoshi OGURI,  

[Date]2010/5/6
[Paper #]RECONF2010-9
Detecting patterns in various size and angle using FPGA

Masayuki SUZUKI,  Yoshifumi TANIDA,  Tsutomu MARUYAMA,  

[Date]2010/5/6
[Paper #]RECONF2010-10
An FPGA Implementation of Tracking Control System with Vibration Control

Yasuaki TEZUKA,  Shuichi ICHIKAWA,  Yoshiyuki NODA,  

[Date]2010/5/6
[Paper #]RECONF2010-11
Software-Hardware Communication and Remote Call on a PC-FPGA Hybrid Cluster

Masaki KOHATA,  Akira UEJIMA,  Ryo OZAKI,  

[Date]2010/5/6
[Paper #]RECONF2010-12
GALS Design for Scalable Array Processors Operating on Multiple FPGAs

Luzhou WANG,  Kentaro SANO,  Satoru YAMAMOTO,  

[Date]2010/5/6
[Paper #]RECONF2010-13
Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System

Akira KOJIMA,  Kazuya TOKUNAGA,  Tetsuo HIRONAKA,  

[Date]2010/5/6
[Paper #]RECONF2010-14
An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs

Yasuaki ITO,  Koji NAKANO,  

[Date]2010/5/6
[Paper #]RECONF2010-15
Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform

Hirokazu MORISHITA,  Kenta INAKAGATA,  Yasunori OSANA,  Naoyuki FUJITA,  Hideharu AMANO,  

[Date]2010/5/6
[Paper #]RECONF2010-16
A translational system using dynamic reconfigurable processor

Kei KINOSHITA,  Daisuke TAKANO,  Tomoyuki OKAMURA,  Tetsuhiko YAO,  Yoshiki YAMAGUCHI,  

[Date]2010/5/6
[Paper #]RECONF2010-17
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[Date]2010/5/6
[Paper #]
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