IEICE Technical Committee

Engineering Sciences/NOLTA-Reliability(Date:2009/09/10)

Presentation

表紙

[Date]2009/9/10
[Paper #]

Real-time detection of rotated patterns using FPGA

Yoshifumi TANIDA, Tsutomu MARUYAMA,

[Date]2009/9/10
[Paper #]RECONF2009-19

Component Labeling on the FPGA using Few Logic Elements

Yasuaki ITO, Koji NAKANO,

[Date]2009/9/10
[Paper #]RECONF2009-20

Performance Evaluation of Levenshtein-Distance Computation on One-Dimensional FPGA Array Cube

Masato YOSHIMI, Mitsunori MIKI, Yuri NISHIKAWA, Akihiro SHITARA, Hideharu AMANO, Oskar MENCER,

[Date]2009/9/10
[Paper #]RECONF2009-21

FPGA implementation and accuracy evaluation of a power-supply voltage control circuit

Masato SOEJIMA, Jyunya SAKEMI, Yuichiro SHIBATA, Fujio KUROKAWA, Tsuyoshi HAMADA, Tomonari MASADA, Kiyoshi OGURI,

[Date]2009/9/10
[Paper #]RECONF2009-22

Low-power oriented clustering and placement tools using routability for FPGAs

Shinya IMAIZUMI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2009/9/10
[Paper #]RECONF2009-23

An analysis of frequency in the use LUT logic functions based on P-equivalence class

Masaki SHINTANI, Kota KATO, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2009/9/10
[Paper #]RECONF2009-24

Design and Evaluation of Flex Power FPGA with Power Reconfigurability

Masakazu HIOKI, Takashi KAWANAMI, Yohei MATSUMOTO, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA, Hanpei KOIKE,

[Date]2009/9/10
[Paper #]RECONF2009-25

Leakage Power Reduction of a Dynamically Reconfigurable Processor with Deal Vth cells

Hideharu AMANO, Keiichiro HIRAI, Toru SANO, Masaru KATO, Yoshiki SAITO,

[Date]2009/9/10
[Paper #]RECONF2009-26

YAWARA : A Self-Optimizing Computer System Project

Takanobu BABA, Kanemitsu OOTSU, Takashi YOKOTA,

[Date]2009/9/10
[Paper #]RECONF2009-27

A Proposal for a Method to Generate an Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation

Yasuhiro NISHINAGA, Ken'ichi UMEDA, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2009/9/10
[Paper #]RECONF2009-28

Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE

Ken'ichi UMEDA, Yasuhiro NISHINAGA, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2009/9/10
[Paper #]RECONF2009-29

Comparsion and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2

Naomichi FURUSHIMA, Nobuya WATANABE, Akira NAGOYA,

[Date]2009/9/10
[Paper #]RECONF2009-30

A Study of Scalable Prototyping System with Small-sized FPGAs

Shimpei WATANABE, Shinya TAKAMAEDA, Ken KYOU, Takefumi MIYOSHI, Kenji KISE,

[Date]2009/9/10
[Paper #]RECONF2009-31

An FPGA-based Tiny Processing System for Small Embedded System and Education

Koji NAKANO, Yasuaki ITO, Kensuke KAWAKAMI, Koji SHIGEMOTO,

[Date]2009/9/10
[Paper #]RECONF2009-32

A Study of Topology-adaptive Network-on-Chip for Many-Core SoC

Hiroshi KADOTA, Akiyoshi WAKATANI,

[Date]2009/9/10
[Paper #]RECONF2009-33

Packet Capturing and Routing Functions on a Network Testbed GtrcNET-10p3

Yuetsu KODAMA, Ryousei TAKANO, Fumihiro OKAZAKI, Tomohiro KUDOH,

[Date]2009/9/10
[Paper #]RECONF2009-34

High-density Implementation for Reconfigurable Device MPLD

Hiroaki TOGUCHI, Masanori ASAEDA, Yutaro ODA, Naoki HIRAKAWA, Kazuya TANIGAWA, Tetsuo HIRONAKA, Masayuki SATO, Takashi ISHIGURO,

[Date]2009/9/10
[Paper #]RECONF2009-35

An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters

Shota ISHIHARA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA,

[Date]2009/9/10
[Paper #]RECONF2009-36