Engineering Sciences/NOLTA-Reliability(Date:2008/01/10)

Presentation
表紙

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[Date]2008/1/10
[Paper #]
目次

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[Date]2008/1/10
[Paper #]
正誤表

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[Date]2008/1/10
[Paper #]
ICCAD summary report

Yusuke MATSUNAGA,  

[Date]2008/1/10
[Paper #]VLD2007-118,CPSY2007-61,RECONF2007-64
A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed-Register Architectures

Tetsuya ENDO,  Akira OHCHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/1/10
[Paper #]VLD2007-119,CPSY2007-62,RECONF2007-65
Memory Binding and Scheduling in High Level Synthesis for FPGAs

Yuki SAGAWA,  Tsuyoshi SADAKATA,  Yusuke MATSUNAGA,  

[Date]2008/1/10
[Paper #]VLD2007-120,CPSY2007-63,RECONF2007-66
Improvement in data communication between PEs for SIMD type processor MX CORE

Yuta MIZOKAMI,  Mitsutaka NAKANO,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2008/1/10
[Paper #]VLD2007-121,CPSY2007-64,RECONF2007-67
Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation

Takahiro KAWAHARA,  Shinobu MIWA,  Hajime SHIMADA,  Shin-ichiro MORI,  Shinji TOMITA,  

[Date]2008/1/10
[Paper #]VLD2007-122,CPSY2007-65,RECONF2007-68
Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication

Shotaro SAITO,  Yasufumi SUGIMORI,  Yoshinori KOHAMA,  Tadahiro KURODA,  Yohei HASEGAWA,  Hideharu AMANO,  

[Date]2008/1/10
[Paper #]VLD2007-123,CPSY2007-66,RECONF2007-69
An effective data I/O mechanism utilizing FIFOs for an array processor

Yuusuke NOMOTO,  Yuka SATO,  Toshiaki MIYAZAKI,  

[Date]2008/1/10
[Paper #]VLD2007-124,CPSY2007-67,RECONF2007-70
Analysis of retention time under continuous reconfiguration of a DORGA.

Daisaku SETO,  Minoru WATANABE,  

[Date]2008/1/10
[Paper #]VLD2007-125,CPSY2007-68,RECONF2007-71
A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array

Mao NAKAJIMA,  Minoru WATANABE,  

[Date]2008/1/10
[Paper #]VLD2007-126,CPSY2007-69,RECONF2007-72
Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays.

Koji SHINOHARA,  Minoru WATANABE,  

[Date]2008/1/10
[Paper #]VLD2007-127,CPSY2007-70,RECONF2007-73
A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability

Shin'ichi KOUYAMA,  Masayuki HIROMORO,  Hiroyuki OCHI,  Yukihiro NAKAMURA,  

[Date]2008/1/10
[Paper #]VLD2007-128,CPSY2007-71,RECONF2007-74
Functionally-partitioned JPEG Decoder for Partial Dynamic Reconfiguration

Taiichiro YATSUNAMI,  Hideaki YOSHIHIRO,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2008/1/10
[Paper #]VLD2007-129,CPSY2007-72,RECONF2007-75
A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor

TUAN Vu MANH,  Hideharu AMANO,  

[Date]2008/1/10
[Paper #]VLD2007-130,CPSY2007-73,RECONF2007-76
An L1 Data Cache Optimization Algorithm for Application Processor Cores

Nobuaki TOJO,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/1/10
[Paper #]VLD2007-131,CPSY2007-74,RECONF2007-77
A Processor Kernel Generation Method for Application-specific Processors

Toshihiro HIURA,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/1/10
[Paper #]VDL2007-132,CPSY2007-75,RECONF2007-78
A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator

Farhad Mehdipour,  Hamid Noori,  Hiroaki Honda,  Koji Inoue,  Kazuaki Murakami,  

[Date]2008/1/10
[Paper #]VDL2007-133,CPSY2007-76,RECONF2007-79
VLIW Extension of Software Development Environment Construction Tool ArchC

Takanori MORIMOTO,  Takahiro KUMURA,  Nagisa ISHIURA,  Masao IKEKAWA,  Masaharu IMAI,  

[Date]2008/1/10
[Paper #]VLD2007-134,CPSY2007-77,RECONF2007-80
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