Engineering Sciences/NOLTA-Reliability(Date:2006/11/23)

Presentation
表紙

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[Date]2006/11/23
[Paper #]
目次

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[Date]2006/11/23
[Paper #]
A Design of AES S-BOX circuit for DPA countermeasure

Minoru SASAKI,  Keisuke IWAI,  Takakazu KUROKAWA,  

[Date]2006/11/23
[Paper #]RECONF2006-44
Development and evaluation of virus check system using FPGA

Yukari ISHIDA,  Yosuke IIJIMA,  Eiichi TAKAHASHI,  Tatsumi FURUYA,  Tetsuya HIGUCHI,  

[Date]2006/11/23
[Paper #]RECONF2006-45
A template matching circuit using with hwObjects including reconfigurable processing circuits

Rika SATO,  Kenji KUDO,  Masatoshi SEKINE,  

[Date]2006/11/23
[Paper #]RECONF2006-46
Design Method of Radix Converters Using Arithmetic Decompositions (2)

Yukihiro IGUCHI,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2006/11/23
[Paper #]RECONF2006-47
Architecture for Numerical Function Generators Using EVBDDs

Shinobu NAGAYAMA,  Tsutomu SASAO,  Jon T. BUTLER,  

[Date]2006/11/23
[Paper #]RECONF2006-48
Consideration about Reconfigurable Architecture based on Digit Serial Arithmetics

Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2006/11/23
[Paper #]RECONF2006-49
A Low-Power Technique using Resource Sharing Approach for Multi-Context Device

Hideaki MONJI,  Hiroshi SHINOHARA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2006/11/23
[Paper #]RECONF2006-50
Area-Efficient Reconfigurable Architecture for Media Processing

Kazuma TAKAHASHI,  Yukio MITSUYAMA,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]2006/11/23
[Paper #]RECONF2006-51
Performance Evaluation of Multi-core DRP for Stream Application

Naohiro KATSURA,  Yohei HASEGAWA,  Vu MANH TUAN,  Hiroki MATSUTANI,  Hideharu AMANO,  

[Date]2006/11/23
[Paper #]RECONF2006-52
Development of Benchmark Test for comparing Dynamic Reconfigurable Architectures

Tetsuya ZUYAMA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2006/11/23
[Paper #]RECONF2006-53
An example of function sharing implementation for reconfigurable system

Hideaki YOSHIHIRO,  Takeru KISANUKI,  Taiichirou YATSUNAMI,  Yukinobu KIYOTA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2006/11/23
[Paper #]RECONF2006-54
Delay Optimized Technology Mapping for Variable Grain Logic Cell

Hideaki NAKAYAMA,  Ryoichi YAMAGUCHI,  Motoki AMAGASAKI,  Kazunori MATSUYAMA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2006/11/23
[Paper #]RECONF2006-55
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[Date]2006/11/23
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[Date]2006/11/23
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[Date]2006/11/23
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