Engineering Sciences/NOLTA-Nonlinear Problems(Date:2000/02/04)

Presentation
表紙

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[Date]2000/2/4
[Paper #]
目次

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[Date]2000/2/4
[Paper #]
On the Recalling Rates of Morphological Associative Memory

T. IDA,  Ke. ZHANG,  T. FUCHIDA,  S. MURASHIMA,  

[Date]2000/2/4
[Paper #]NLP99-136
Cellular Neural Networks with Hysteresis cell(The Second Report)

Keiko NAKAYAMA,  Michihiro NAMBA,  Hiroaki KAWABATA,  Akihiro KANAGAWA,  Zhong ZHANG,  

[Date]2000/2/4
[Paper #]NLP99-137
Hysteresis Cellular Automata.

Takumi Saito,  Kenya Jin'no,  Haruo Hirose,  

[Date]2000/2/4
[Paper #]NLP99-138
An Electronic Circuit Experiment of Explosion and Intermittency Observed from a Forced PLL Circuit

Toshiharu Ooi,  Wataru Ohno,  Tetsuro Endo,  

[Date]2000/2/4
[Paper #]NLP99-139
Synchronization Phenomena of Oscillator Containing N-Type Negative Conductance

Yoshihiro Miyano,  Junichi Fujita,  Shinsaku Mori,  Seiichiro Moro,  

[Date]2000/2/4
[Paper #]NLP99-140
Mutual Cross Coupled Two Chaotic Oscillators

Yuuki Itou,  Shinsaku Mori,  

[Date]2000/2/4
[Paper #]NLP99-141
A Discrete-time Neural Network for Multi-Layer Channel Routing Problems.

Tsuyoshi Iwata,  Kenya Jin'no,  Haruo Hirose,  

[Date]2000/2/4
[Paper #]NLP99-142
A Method of Solving the Scheduling Problem by Hopfeild Network Learning

Zheng Tang,  Nobuhiko Muta,  HaiHe Jin,  

[Date]2000/2/4
[Paper #]NLP99-143
The Optimization problems in imege processing by Hopfield Network Learning

Zheng Tang,  Yoshitaka Sasaki,  HaiHe Jin,  

[Date]2000/2/4
[Paper #]NLP99-144
A Method of Solving N-Queen Problem by Hopfield Network Learning

Hiroo Kumagai,  Zheng Tang,  HaiHe Jin,  

[Date]2000/2/4
[Paper #]NLP99-145
Finding All Solutions of Piecewise-Linear Circuits

Shigeru TANAKA,  Kiyotaka YAMAMURA,  

[Date]2000/2/4
[Paper #]NLP99-146
Characteristics of FG-MOS on the standard CMOS process

Motoi Inaba,  Takahiko Tsutsumi,  Yutaka Ono,  Koichi Tanno,  Okihiko Ishizuka,  

[Date]2000/2/4
[Paper #]NLP99-147
Design and analysis of Neuron-MOS Down Literal Circuits

Jing Shen,  Masashi Nagasato,  Koichi Tanno,  Okihiko Ishizuka,  

[Date]2000/2/4
[Paper #]NLP99-148
Multi-Input Variable-Threshold Circuits with Neuron-MOS transistor

Makoto Syuto,  Hiroshi Magata,  Koichi Tanno,  Okihiko Ishizuka,  

[Date]2000/2/4
[Paper #]NLP99-149
[OTHERS]

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[Date]2000/2/4
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