Engineering Sciences/NOLTA-Hardware Security(Date:2021/03/03)

Presentation
[Memorial Lecture] Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture

Mingfei Yu(Univ. Tokyo),  Ruitao Gao(Univ. Tokyo),  Masahiro Fujita(Univ. Tokyo),  

[Date]2021-03-03
[Paper #]VLD2020-71,HWS2020-46
Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing

Yoshinori Ono(SIT),  Kimiyoshi Usami(SIT),  

[Date]2021-03-03
[Paper #]VLD2020-67,HWS2020-42
[Memorial Lecture] Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization

TaiYu Cheng(Osaka Univ.),  Yutaka Masuda(Nagoya Univ.),  Jun Nagayama(Socionext Inc.),  Yoichi Momiyama(Socionext Inc.),  Jun Chen(Osaka Univ.),  Masanori Hashimoto(Osaka Univ.),  

[Date]2021-03-03
[Paper #]VLD2020-72,HWS2020-47
A performance and resources estimation of AI Inference circuit on FPGAs

Ryo Yamamoto(MELCO),  Iwagawa Hidetoshi(MELCO),  Yoshihiro Ogawa(MELCO),  

[Date]2021-03-03
[Paper #]VLD2020-69,HWS2020-44
Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems

Iori Muguruma(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Takuya Ando(Kwansei Gakuin Univ.),  Hiroyuki Tomiyama(Ritsumeikan Univ.),  Hiroyuki Kanbara(ASTEM RI/KYOTO),  

[Date]2021-03-03
[Paper #]VLD2020-75,HWS2020-50
Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems

Takuma Hikida(Ritsumeikan Univ.),  Hiroki Nishikawa(Ritsumeikan Univ.),  Hiroyuki Tomiyama(Ritsumeikan Univ.),  

[Date]2021-03-03
[Paper #]VLD2020-76,HWS2020-51
The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation

Masato Kiyama(Kumamoto Univ.),  Yasuhiro Nakahara(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  

[Date]2021-03-03
[Paper #]VLD2020-70,HWS2020-45
Evaluation on Approximate Multiplier for CNN Calculation

Yuechuan Zhang(UTokyo),  Masahiro Fujita(UTokyo),  Takashi Matsumoto(UTokyo),  

[Date]2021-03-03
[Paper #]VLD2020-68,HWS2020-43
Highly Efficient Simulation Method to Find Hardware Trojans Hidden in Semiconductor Chips

Kazuki Yasuda(Kobe Univ.),  Kazuki Monta(Kobe Univ.),  Daichi Nakagawa(Kobe Univ.),  Masaru Mashiba(Kobe Univ.),  Takuji Miki(Kobe Univ.),  Makoto Nagata(Kobe Univ.),  

[Date]2021-03-03
[Paper #]VLD2020-77,HWS2020-52
Measurement of Voltage-variation-tolerant Temperature Sensor for Standard CMOS Chip with On-chip Solar Cell

Shuto Murohara(Ritsumeikan Univ.),  Tatsuya Banno(Ritsumeikan Univ.),  Tomoya Kimura(Ritsumeikan Univ.),  Takashi Imagawa(Ritsumeikan Univ.),  Hiroyuki Ochi(Ritsumeikan Univ.),  

[Date]2021-03-03
[Paper #]VLD2020-74,HWS2020-49
Counteracting Chip Transplantation Attack using Hologram on Epoxy Covering

Takashi Sudo(UEC),  Takeshi Sugawara(UEC),  

[Date]2021-03-03
[Paper #]VLD2020-78,HWS2020-53
[Memorial Lecture] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures

Atsushi Matsuo(Ritsumeikan University),  Wakaki Hattori(Ritsumeikan University),  Shigeru Yamashita(Ritsumeikan University),  

[Date]2021-03-03
[Paper #]VLD2020-73,HWS2020-48
Design space exploration on low energy embedded multi-core processors

Sayuri Onagi(Tokyo Tech),  Yuko Hara(Tokyo Tech),  

[Date]2021-03-04
[Paper #]VLD2020-79,HWS2020-54
FPGA Implementation of Lightweight Cipher Chaskey through High-Level Synthesis and its Evaluation of Side-Channel Attack Resistance

Saya Inagaki(Tokyo Tech),  Mingyu Yang(Tokyo Tech),  Yang Li(UEC),  Kazuo Sakiyama(UEC),  Yuko Hara(Tokyo Tech),  

[Date]2021-03-04
[Paper #]VLD2020-86,HWS2020-61
Security Evaluation of an IoT Cloud Service against Local Attacks

Makoto Ishida(UEC),  Takeshi Sugawara(UEC),  

[Date]2021-03-04
[Paper #]VLD2020-89,HWS2020-64
High-level synthesis of approximate circuits with two-level accuracies

Kenta Shirane(Ritumeikan Univ.),  Hiroki Nishikawa(Ritumeikan Univ.),  Xiangbo Kong(Ritumeikan Univ.),  Hiroyuki Tomiyama(Ritumeikan Univ.),  

[Date]2021-03-04
[Paper #]VLD2020-80,HWS2020-55
Design of Area-Efficient Response Generator for CMOS Image Sensor PUF

Masanori Aoki(Ritsumeikan Univ.),  Shunsuke Okura(Ritsumeikan Univ.),  Masayoshi Shirahata(Ritsumeikan Univ.),  Takeshi Fujino(Ritsumeikan Univ.),  

[Date]2021-03-04
[Paper #]VLD2020-82,HWS2020-57
A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design

Maya Oda(Tohoku Univ.),  Rei Ueno(Tohoku Univ.),  Naofumi Homma(Tohoku Univ.),  Akiko Inoue(NEC),  Kazuhiko Minematsu(NEC),  

[Date]2021-03-04
[Paper #]VLD2020-83,HWS2020-58
Survey on intrusion detection system for Vehicle Security Techniques

Ayaka Matsushita(IISEC),  Takao Okubo(IISEC),  

[Date]2021-03-04
[Paper #]VLD2020-88,HWS2020-63
Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings

Ayano Nakashima(Tohoku Univ.),  Rei Ueno(Tohoku Univ.),  Naofumi Homma(Tohoku Univ.),  

[Date]2021-03-04
[Paper #]VLD2020-84,HWS2020-59
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