IEICE Technical Committee

Engineering Sciences/NOLTA-Hardware Security(Date:2019/02/27)

Presentation

Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis

Masato Tatsuoka(JAIST), Mineo Kaneko(JAIST),

[Date]2019-02-27
[Paper #]VLD2018-96,HWS2018-59

A Case Study on Approximate Multipliers for MNIST CNN

Kenta Shirane(Ritsumeikan Univ.), Takahiro Yamamoto(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2019-02-27
[Paper #]VLD2018-95,HWS2018-58

A Battery Degradation aware System Level Battery Management Methodology

Daichi Watari(Osaka Univ.), Ittetsu Taniguchi(Osaka Univ.), Takao Onoye(Osaka Univ.),

[Date]2019-02-27
[Paper #]VLD2018-104,HWS2018-67

Function-level Module Sharing with High-level Synthesis

Ryohei Nozaki(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2019-02-27
[Paper #]VLD2018-100,HWS2018-63

High-Level Synthesis of the CHStone Benchmark Programs with SDSoC

Takuya Adachi(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2019-02-27
[Paper #]VLD2018-101,HWS2018-64

Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory

Seiya Shirakuni(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2019-02-27
[Paper #]VLD2018-105,HWS2018-68

Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework

Masataka Aoki(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu),

[Date]2019-02-27
[Paper #]VLD2018-102,HWS2018-65

Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA

Asuka Natsuhara(Ritsumeikan Univ.), Takashi Imagawa(Ritsumeikan Univ.), Hiroyuki Ochi(Ritsumeikan Univ.),

[Date]2019-02-27
[Paper #]VLD2018-97,HWS2018-60

Routing Algorithm to Achieve Circular Wire for SIM-Type SADP

Shun Akatsuka(TUAT), Kunihiro Fujiyoshi(TUAT),

[Date]2019-02-27
[Paper #]VLD2018-98,HWS2018-61

Timing Correction by Constrained Temperature Dependent Clock Skew

Mineo Kaneko(JAIST),

[Date]2019-02-27
[Paper #]VLD2018-103,HWS2018-66

Improvement on DMA Transfer Efficiency by Packet Concatenation

Shoko Ohteru(NTT), Saki Hatta(NTT), Tomoaki Kawamura(NTT), Koji Yamazaki(NTT), Takahiro Hatano(NTT), Akihiko Miyazaki(NTT), Koyo Nitta(NTT),

[Date]2019-02-27
[Paper #]VLD2018-106,HWS2018-69

Set-Pair Routing Algorithm with Selective Pin-Pair Connections

Kano Akagi(Tokyo Tech), Shimpei Sato(Tokyo Tech), Atsushi Takahashi(Tokyo Tech),

[Date]2019-02-27
[Paper #]VLD2018-99,HWS2018-62

FPGA Implementation of Fully Convolutional Network for Semantic Segmentation

Masayuki Shimoda(titech), Youki Sada(titech), Hiroki Nakahara(titech),

[Date]2019-02-27
[Paper #]VLD2018-93,HWS2018-56

Spatial-Separable Convolution: Low memory CNN for FPGA

Akira Jinguji(titech), Masayuki Shimoda(titech), Hiroki Nakahara(titech),

[Date]2019-02-27
[Paper #]VLD2018-94,HWS2018-57

凍結ビットパタン分岐によるリストサイズ2のポーラ符号高速リストデコーダ

Yuka Aizawa(Waseda Univ.), Masashi Tawada(Waseda Univ.), Yuta Ideguchi(NEC), Norifumi Kamiya(NEC), Nozomu Togawa(Waseda Univ.),

[Date]2019-02-28
[Paper #]VLD2018-111,HWS2018-74

A SPICE Model Parameter Extraction Environment Using Automatic Differentiation

Aoi Ueda(NNCT), Michihiro Shintani(NAIST), Hiroshi Iwata(NNCT), Ken'ichi Yamaguchi(NNCT), Michiko Inoue(NAIST),

[Date]2019-02-28
[Paper #]VLD2018-117,HWS2018-80

Thermal transient analysis and evaluation of the heat generation and dissipation in three-dimensional stacked LSI

Ryota Horigome(Shibaura Inst. of Tech.), Kimiyoshi Usami(Shibaura Inst. of Tech.),

[Date]2019-02-28
[Paper #]VLD2018-107,HWS2018-70

Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB

Ryo Magasaki(Shibaura Inst. of Tech.), Yusuke Yoshida(Shibaura Inst. of Tech.), Hideharu Amano(Keio Univ.), Kimiyoshi Usami(Shibaura Inst. of Tech.),

[Date]2019-02-28
[Paper #]VLD2018-108,HWS2018-71

Single Supply Level Shifter Circuit using body-bias

Yuki Takeyoshi(SIT), Kimiyoshi Usame(SIT),

[Date]2019-02-28
[Paper #]VLD2018-109,HWS2018-72

High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology

Kazuki Niino(Ritsumeikan Univ.), Takashi Imagawa(Ritsumeikan Univ.), Hiroyuki Ochi(Ritsumeikan Univ.),

[Date]2019-02-28
[Paper #]VLD2018-112,HWS2018-75