Engineering Sciences/NOLTA-Circuits and Systems(Date:2007/06/15)

Presentation
表紙

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[Date]2007/6/15
[Paper #]
目次

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[Date]2007/6/15
[Paper #]
A Brain Computer Interface Based on FFT and Multilayer Neural Network : Feature Extraction and Generalization

Yasuaki KANEDA,  Kenji NAKAYAMA,  Akihiro HIRANO,  

[Date]2007/6/15
[Paper #]CAS2007-19,VLD2007-35,SIP2007-49
Circuit Theory Using Equivalent Circuits for Motion Equation of Molecules

Nobuo NAGAI,  

[Date]2007/6/15
[Paper #]CAS2007-20,VLD2007-36,SIP2007-50
Asymptotic Behavior and High-Pass Nature of Continuously Varying Nonuniform Transmission Lines as ω Approaches Infinity

Fumio KATO,  

[Date]2007/6/15
[Paper #]CAS2007-21,VLD2007-37,SIP2007-51
A Lateral Unified-CBiCMOS Buffer Circuit for Driving 5nF Maximum Load Capacitance per CCD Clock

Masatoshi KOBAYASHI,  Takashi HAMAHATA,  Toshiro AKINO,  Kenji NISHI,  LE Cuong VO,  Kohsei TAKEHARA,  T.Goji ETOH,  

[Date]2007/6/15
[Paper #]CAS2007-22,VLD2007-38,SIP2007-52
Timing error risk analysis and power grid optimization considering variability of manufacturing

Makoto TERAO,  Kenji KUSANO,  Yoshiyuki KAWAKAMI,  Masahiro FUKUI,  Shuji TSUKIYAMA,  

[Date]2007/6/15
[Paper #]CAS2007-23,VLD2007-39,SIP2007-53
Re-scheduling with Skew Optimization in RT-Datapath Synthesis

Takayuki OBATA,  Mineo KANEKO,  

[Date]2007/6/15
[Paper #]CAS2007-24,VLD2007-40,SIP2007-54
Power Constrained IP Core Wrapper Design with Partitioned Clock Domains

Thomas Edison YU,  Tomokazu YONEDA,  Danella ZHAO,  Hideo FUJIWARA,  

[Date]2007/6/15
[Paper #]CAS2007-25,VLD2007-41,SIP2007-55
Scalable Dual-Radix Unified Montgomery Multiplier in GF(P) and GF(2^n)

Kazuyuki TANIMURA,  Ryuta NARA,  Shunitsu KOHARA,  Youhua SHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/6/15
[Paper #]CAS2007-26,VLD2007-42,SIP2007-56
Arithmetic Module Generation Using Optimized Parallel Prefix Adders

Yuki WATANABE,  Naofumi HOMMA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]2007/6/15
[Paper #]CAS2007-27,VLD2007-43,SIP2007-57
Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems

Masato INAGI,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2007/6/15
[Paper #]CAS2007-28,VLD2007-44,SIP2007-58
Pitch Event Extraction Using Multiple Low-pass Filtering under Noisy Environment

Yoshitaka ONODA,  Nobuhiro MIKI,  

[Date]2007/6/15
[Paper #]CAS2007-29,VLD2007-45,SIP2007-59
Signal channel source separation based on the clustering of periodic sparse codes

Makoto NAKASHIZUKA,  Hiroyuki OKUMURA,  Youji IIGUNI,  

[Date]2007/6/15
[Paper #]CAS2007-30,VLD2007-46,SIP2007-60
A Study on Sound Field Reproduction System Using Simultaneous Perturbation Method

Kazuya TSUKAMOTO,  Yoshinobu KAJIKAWA,  Yasuo NOMURA,  

[Date]2007/6/15
[Paper #]CAS2007-31,VLD2007-47,SIP2007-61
Robust F0 Estimation using Forward and Backward LP based Complex Speech Analysis

Keiichi FUNAKI,  Tatsuhiko KINJO,  

[Date]2007/6/15
[Paper #]CAS2007-32,VLD2007-48,SIP2007-62
A Study on Lossless Steganography for G.711

Naofumi AOKI,  

[Date]2007/6/15
[Paper #]CAS2007-33,VLD2007-49,SIP2007-63
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[Date]2007/6/15
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[Date]2007/6/15
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