Engineering Sciences/NOLTA-Circuits and Systems(Date:2005/06/21)

Presentation
表紙

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[Date]2005/6/21
[Paper #]
目次

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[Date]2005/6/21
[Paper #]
Development of Realtime Player Tracing System with Adaptive Background Renewal

Munehiro TOKIKURA,  Akinori NISHIHARA,  

[Date]2005/6/21
[Paper #]CAS2005-15,VLD2005-26,SIP2005-39
High-Accuracy Motion Estimation for Video Sequences Based on Phase-Only Correlation

Norihito NUMA,  Hui Chien LOY,  Takafumi AOKI,  Satoshi KONDO,  

[Date]2005/6/21
[Paper #]CAS2005-16,VLD2005-27,SIP2005-40
Fast Image Identification for Coded Images with Different Compression Ratio

Ikue IIZUKA,  Fitri Arnia,  Masaaki FUJIYOSHI,  Hitoshi KIYA,  

[Date]2005/6/21
[Paper #]CAS2005-17,VLD2005-28,SIP2005-41
A Scale Estimation Algorithm Based on Phase-Only Correlation for Electron Microscope Images

Sei NAGASHIMA,  Takafumi AOKI,  Ruriko TSUNETA,  

[Date]2005/6/21
[Paper #]CAS2005-18,VLD2005-29,SIP2005-42
A compiler framework to combine multiple code optimization methods

Yuhei Kaneko,  Nobuhiko Sugino,  

[Date]2005/6/21
[Paper #]CAS2005-19,VLD2005-30,SIP2005-43
Optimal Design of Fast Adders Based on Redundant Number Systems

Naofumi HOMMA,  Takahumi AOKI,  Tatsuo HIGUCHI,  

[Date]2005/6/21
[Paper #]CAS2005-20,VLD2005-31,SIP2005-44
Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH

Yuuki WATANABE,  Nofumi HOMMA,  Takahumi AOKI,  Tatsuo HIGUCHI,  

[Date]2005/6/21
[Paper #]CAS2005-21,VLD2005-32,SIP2005-45
A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm

Tatsuyuki ISHIKAWA,  Kazunori SHIMIZU,  Takeshi IKENAGA,  Satoshi GOTO,  

[Date]2005/6/21
[Paper #]CAS2005-22,VLD2005-33,SIP2005-46
High Driving Capability by Lateral Unified CBiCMOS Inverter with Resistor-Ratio Type Control Circuits

Takashi Hamahata,  Toshiro Akino,  

[Date]2005/6/21
[Paper #]CAS2005-23,VLD2005-34,SIP2005-47
Design and Evaluation of a Bit-Parallel Magnitude-Comparison CAM Based on TMR Logic

Kohei SHOJI,  Takahiro HANYU,  

[Date]2005/6/21
[Paper #]CAS2005-24,VLD2005-35,SIP2005-48
Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI

Shoun MATSUNAGA,  Takahiro HANYU,  

[Date]2005/6/21
[Paper #]CAS2005-25,VLD2005-36,SIP2005-49
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[Date]2005/6/21
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[Date]2005/6/21
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[Date]2005/6/21
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