Engineering Sciences/NOLTA-Circuits and Systems(Date:2002/06/22)

Presentation
表紙

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[Date]2002/6/22
[Paper #]
目次

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[Date]2002/6/22
[Paper #]
Design Rule Extraction from DRC Rule Files, and Its Visualization

Naoki KITAURA,  Hiroyuki OCHI,  Takao TSUDA,  

[Date]2002/6/22
[Paper #]CAS2002-42
A Parasitic Capacitance Modeling Method for Multilevel Interconnects

Sadahiro TANI,  Yoshihiro UCHIDA,  Shuji TSUKIYAMA,  Isao SHIRAKAWA,  

[Date]2002/6/22
[Paper #]CAS2002-43
Method for Phase-Assignment in Automatic Phase-Shift Mask Design

Keitaro Katabuchi,  Eiji Tsujimoto,  Akemi Moniwa,  Takuya Hagiwara,  Yosinobu Igarashi,  

[Date]2002/6/22
[Paper #]CAS2002-44
Construction of Processing Environment with FPGAs and DSPs

Yuhei HAYASHI,  Yuichi IWAYA,  Koichiro TANAKA,  Toshinori SATO,  Itsujiro ARITA,  

[Date]2002/6/22
[Paper #]CAS2002-45
Proposal of Common Processor Architecture Description for ASIP Design Automation : Integration of Processor and Machine Description for Retargetable Compiler

Nobuyuki HIKICHI,  Shinsuke KOBAYASHI,  Kentaro MIATA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2002/6/22
[Paper #]CAS2002-46
Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors

Hiroshi UCHIDA,  Yosuke MITANI,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  Tetsuo HIRONAKA,  

[Date]2002/6/22
[Paper #]CAS2002-47
Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory

Seiji FUKAE,  Nobuhiko OMORI,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  Tomohiro INOUE,  Tetsuo HIRONAKA,  

[Date]2002/6/22
[Paper #]CAS2002-48
[OTHERS]

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[Date]2002/6/22
[Paper #]