Engineering Sciences/NOLTA-Circuits and Systems(Date:1993/05/20)

Presentation
目次

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[Date]1993/5/20
[Paper #]
[CATALOG]

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[Date]1993/5/20
[Paper #]
Design of Observer-based Adaptive Controller for Uncertain Systems

Midori Maki,  Kojiro Hagino,  

[Date]1993/5/20
[Paper #]CAS93-1,VLD93-1,DSP93-11
Optimum Lower Bound for Lipschitzian Optimization

Isao Yamada,  Kohichi Sakaniwa,  Shigeo Tsujii,  

[Date]1993/5/20
[Paper #]CAS93-2,VLD93-2,DSP93-12
A steady state analysis method of nonlinear circuit with multi- port excitations

Satoshi Ichikawa,  

[Date]1993/5/20
[Paper #]CAS93-3,VLD93-3,DSP93-13
Poles and Zeros of the Reflection Coefficient in the Quantum Scattering Rroblem

Fumio Kato,  

[Date]1993/5/20
[Paper #]CAS93-4,VLD93-4,DSP93-14
Formulation of Scattering Effect on Resonant Tunneling Coused by Some Undecided Factors Based on Network Theory

Naoki Ohtani,  Nobuo Nagai,  Masakiyo Suzuki,  Nobuhiro Miki,  

[Date]1993/5/20
[Paper #]CAS93-5,VLD93-5,DSP93-15
Considerations of relations between RLS method and ARMA latice filter algorithm

Miki Haseyama,  Nobuo Nagai,  Nobuhiro Miki,  

[Date]1993/5/20
[Paper #]CAS93-6,VLD93-6,DSP93-16
A Routing Design Method for Analog PCB using Surface Charge Modeling

Isamu Konta,  Masatoshi Kasuga,  Jin-ichi Matsuda,  

[Date]1993/5/20
[Paper #]CAS93-7,VLD93-7,DSP93-17
Extension of greedy channel router to 3D model in VLSI layout design

Michiroh Ohmura,  

[Date]1993/5/20
[Paper #]CAS93-8,VLD93-8,DSP93-18
A Delay Minimized Zero-Skew Clock Routing with Wire Width Optimization

Midori Takano,  Fumihiro Minami,  Naohito Kojima,  Takashi Mitsuhashi,  

[Date]1993/5/20
[Paper #]CAS93-9,VLD93-9,DSP93-19
A Parallel Processing Method of LSI Design Rule Check Dividing The Layout Pattern into Multi-Domain

Tatsuo Uesaka,  Hiroshi Ikeda,  Ichiro Kouno,  Keimei Lu,  Keikichi Tamaru,  

[Date]1993/5/20
[Paper #]CAS93-10,VLD93-10,DSP93-20
Compaction with Shape Optimization

Kazuhisa Okada,  Hidetoshi Onodera,  Keikichi Tamaru,  

[Date]1993/5/20
[Paper #]CAS93-11,VLD93-11,DSP93-21
A VSELP CODEC DSP using 0.5μm CMOS standard cell

Teruo Ishihara,  Noboru Kobayashi,  Shokichi Mori,  Kiyoshi Utsugi,  Yoshio Kajii,  Tsuyoshi Yamamura,  Shinji Sugatani,  Yasuji Shigihara,  Tomohiko Taniguchi,  Atsuyuki Mukai,  

[Date]1993/5/20
[Paper #]CAS93-12,VLD93-12,DSP93-22
Multi Project Chip Services for Universities in Europe and America

Kazuhiro Ueda,  

[Date]1993/5/20
[Paper #]CAS93-13,VLD93-13,DSP93-23
[OTHERS]

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[Date]1993/5/20
[Paper #]