Electronics-Silicon Devices and Materials(Date:2016/01/28)

Presentation
[Invited Talk] Experimental Study on Carrier Transport Properties in Extremely-Thin Body Ge-on-Insulator (GOI) p-MOSFETs with GOI Thickness Down to 2 nm

Xiao Yu(Univ. of Tokyo),  Jian Kang(Univ. of Tokyo),  Mitsuru Takenaka(Univ. of Tokyo),  Shinichi Takagi(Univ. of Tokyo),  

[Date]2016-01-28
[Paper #]SDM2015-120
[Invited Talk] Carrier Transport Analysis of High-Performance Poly-Si Nanowire Transistor Fabricated by Advanced SPC with Record-High Electron Mobility

Minoru Oda(Toshiba Corp.),  Kiwamu Sakuma(Toshiba Corp.),  Yuuichi Kamimuta(Toshiba Corp.),  Masumi Saitoh(Toshiba Corp.),  

[Date]2016-01-28
[Paper #]SDM2015-121
[Invited Talk] Understanding of BTI for Tunnel FETs

Wataru Mizubayashi(AIST),  Takahiro Mori(AIST),  Koichi Fukuda(AIST),  Yuki Ishikawa(AIST),  Yukinori Morita(AIST),  Shinji Migita(AIST),  Hiroyuki Ota(AIST),  Yongxun Liu(AIST),  Shinichi O'uchi(AIST),  Junichi Tsukada(AIST),  Hiromi Yamauchi(AIST),  Takashi Matsukawa(AIST),  Meishoku Masahara(AIST),  Kazuhiko Endo(AIST),  

[Date]2016-01-28
[Paper #]SDM2015-122
[Invited Talk] Van der Waals Junctions of Layered 2D Materials for Functional Devices

Tomoki Machida(Univ. of Tokyo),  Rai Moritani(Univ. of Tokyo),  Yohta Sata(Univ. of Tokyo),  Takehiro Yamaguchi(Univ. of Tokyo),  Miho Arai(Univ. of Tokyo),  Naoto Yabuki(Univ. of Tokyo),  Sei Morikawa(Univ. of Tokyo),  Satoru Masubuchi(Univ. of Tokyo),  Keiji Ueno(Saitama Univ.),  

[Date]2016-01-28
[Paper #]SDM2015-123
[Invited Talk] CMOS photonics technologies based on heterogeneous integration on Si

Mitsuru Takenaka(Univ. of Tokyo),  Younghyun Kim(Univ. of Tokyo),  Jaehoon Han(Univ. of Tokyo),  Jian Kan(Univ. of Tokyo),  Yuki Ikku(Univ. of Tokyo),  Yongpeng Cheng(Univ. of Tokyo),  Jinkwon Park(Univ. of Tokyo),  SangHyeon Kim(Univ. of Tokyo),  Shinichi Takagi(Univ. of Tokyo),  

[Date]2016-01-28
[Paper #]SDM2015-124
[Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes

Koji Nii(Renesas),  Makoto Yabuuchi(Renesas),  Yoshisato Yokoyama(Renesas System Design),  Yuichiro Ishii(Renesas),  Takeshi Okagaki(Renesas),  Masao Morimoto(Renesas),  Yasumasa Tsukamoto(Renesas),  Koji Tanaka(Renesas System Design),  Miki Tanaka(Renesas System Design),  Shinji Tanaka(Renesas),  

[Date]2016-01-28
[Paper #]SDM2015-125
[Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme

Kazutaka Ikegami(Toshiba),  Hiroki Noguchi(Toshiba),  Satoshi Takaya(Toshiba),  Chikayoshi Kamata(Toshiba),  Minoru Amano(Toshiba),  Keiko Abe(Toshiba),  Keiichi Kushida(Toshiba),  Eiji Kitagawa(Toshiba),  Takao Ochiai(Toshiba),  Naoharu Shimomura(Toshiba),  Daisuke Saida(Toshiba),  Atsushi Kawasumi(Toshiba),  Hiroyuki Hara(Toshiba),  Junichi Ito(Toshiba),  Shinobu Fujita(Toshiba),  

[Date]2016-01-28
[Paper #]SDM2015-126
[Invited Talk] Super Steep Subthreshold Slope PN-Body Tied SOI FET with Ultra Low Drain Voltage

Jiro Ida(Kanazawa Institute of Technology),  

[Date]2016-01-28
[Paper #]SDM2015-127