Electronics-Silicon Devices and Materials(Date:2010/01/29)

Presentation
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[Date]2010/1/29
[Paper #]
目次

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[Date]2010/1/29
[Paper #]
Key Issues and Future Prospect for 3-D Integration Technology

Mitsumasa KOYANAGI,  Takafumi FUKUSHIMA,  Kang-Wook LEE,  Tetsu TANAKA,  

[Date]2010/1/29
[Paper #]SDM2009-182
Highly-Reliable Cu Interconnect covered with CoWB Metal-cap in a Waterproof Molecular-Pore-Stack (MPS)-SiOCH film

Yoshihiro Hayashi,  Masayoshi Tagami,  Inoue Naoya /,  Emiko Nakazawa,  Kouji Arita,  

[Date]2010/1/29
[Paper #]SDM2009-183
Feasibility Study of 60nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation

N. Nakamura,  N. Oda,  E. Soda,  N. Hosoi,  A Gawase,  H. Aoyama,  Y. Tanaka,  D. Kawamura,  S. Chikaki,  M. Shiohara,  N. Tarumi,  S. Kondo,  I. Mori,  S. Saito,  

[Date]2010/1/29
[Paper #]SDM2009-184
Advanced Direct-CMP Process for Porous Low-k Thin Film

H. Korogi,  H. Chibahara,  S. Suzuki,  M. Tsutsue,  K. Seo,  Y. Oka,  K. Goto,  M. Akazawa,  H. Miyatake,  S. Matsumoto,  T. Ueda,  

[Date]2010/1/29
[Paper #]SDM2009-185
Optimization of Metallization Processes for 32-nm-node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9)

M. Iguchi,  S. Yokogawa,  H. Aizawa,  Y. Kakuhara,  H. Tsuchiya,  N. Okada,  K. Imai,  M. Tohara,  K. Fujii,  T. Watanabe,  

[Date]2010/1/29
[Paper #]SDM2009-186
Low resistive and highly reliable copper interconnects in combination of silicide-cap Ti-barrier for 32 nm-node and beyond

Yumi HAYASHI,  Noriaki MATSUNAGA,  Makoto WADA,  Shinichi NAKAO,  Atsuko SAKATA,  Kei WATANABE,  Hideki SHIBATA,  

[Date]2010/1/29
[Paper #]SDM2009-187
Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond

Kazuyuki Ohmori,  Kenichi Mori,  Kazuyoshi Maekawa,  Kazuyuki Kohama,  Kazuhiro Ito,  Takashi Ohnishi,  Masao Mizuno,  Koyu Asai,  Masanori Murakami,  Hiroshi Miyatake,  

[Date]2010/1/29
[Paper #]SDM2009-188
Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging

Shintaro Yamamichi,  Kentaro Mori,  Katsumi Kikuchi,  Hideya Murai,  Daisuke Ohshima,  Yoshiki Nakashima,  Koji Soejima,  Masaya Kawano,  Tomoo Murakami,  

[Date]2010/1/29
[Paper #]SDM2009-189
Defects in Cu/low-k Interconnects Probed Using Monoenergetic Positron Beams

Akira UEDONO,  Naoya INOUE,  Yoshiihro HAYASHI,  Kazuhiro EGUCHI,  Tomoji NAKAMURA,  Yukinori HIROSE,  Masaki YOSHIMARU,  Nagayasu OSHIMA,  Toshiyuki OHDAIRA,  Ryoichi SUZUKI,  

[Date]2010/1/29
[Paper #]SDM2009-190
Evaluation of Dielectric Constant through Direct CMP of Porous Low-k Film

Masako KODERA,  Takumi TAKAHAHSI,  Gaku MINAMIHABA,  

[Date]2010/1/29
[Paper #]SDM2009-191
Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns

Atsuko YAMAGUCHI,  Daisuke RYUZAKI,  Ken'ichi TAKEDA,  Hiroki KAWADA,  

[Date]2010/1/29
[Paper #]SDM2009-192
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