Electronics-Silicon Devices and Materials(Date:2009/01/19)

Presentation
表紙

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[Date]2009/1/19
[Paper #]
目次

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[Date]2009/1/19
[Paper #]
Impact of Additional Factors in Threshold Voltage Variability of Metal/High-k Gate Stacks and Its Reduction by Controlling Crystalline Structure and Grain Size in the Metal Gates

K. Ohmori,  T. Matsuki,  D. Ishikawa,  T. Morooka,  T. Aminaka,  Y. Sugita,  T. Chikyow,  K. Shiraishi,  Y. Nara,  K. Yamada,  

[Date]2009/1/19
[Paper #]SDM2008-196
Intrinsic Origin of Electric Dipoles Formed at High-k/SiO_2 Interface

Koji KITA,  Akira Toriumi,  

[Date]2009/1/19
[Paper #]SDM2008-197
Experimental Investigation on the Origin of Direction Dependence of Si(110) Hole Mobility Utilizing Ultra-Thin Body pMOSFETs

Ken SHIMIZU,  Takuya SARAYA,  Toshiro HIRAMOTO,  

[Date]2009/1/19
[Paper #]SDM2008-198
A High-sensitivity Broadband Image Sensor using CuInGaSe_2 Thin Films

Osamu MATSUSHIMA,  Kenichi MIYAZAKI,  Masaki TAKAOKA,  Takuji MAEKAWA,  Hiroaki SHIRAGA,  Hiroshi SEKIGUCHI,  Takaaki FUCHIKAMI,  Masato MORIWAKE,  Hidemi TAKASU,  Shogo ISHIZUKA,  Keiichiro SAKURAI,  Akimasa YAMADA,  Shigeru NIKI,  

[Date]2009/1/19
[Paper #]SDM2008-199
Floating Gate Super Multi Level NAND Flash Memory for 30nm and beyond

T. Kamigaichi,  F. Arai,  H. Nitta,  M. Endo,  K. Nishihara,  T. Murata,  H. Takekida,  T. Izumi,  K. Uchida,  T. Maruyama,  I. Kawabata,  Y. Suyama,  A. Sato,  K. Ueno,  H. Takeshita,  Y. Joko,  S. Watanabe,  Y. Liu,  H. Meguro,  A. Kajita,  Y. Ozawa,  T. Watanabe,  S. Sato,  H. Tomiie,  Y. Kanamaru,  R. Shoji,  C.H. Lai,  M. Nakamichi,  K. Oowada,  T. Ishigaki,  G. Hemink,  D. Dutta,  Y. Dong,  C. Chen,  G. Liang,  M. Higashitani,  J. Lutze,  

[Date]2009/1/19
[Paper #]SDM2008-200
Conformal Doping for FinFETs and Precise Controllable Shallow Doping for Planar FET Manufacturing by a Novel B_2H_6/Helium Self-Regulatory Plasma Doping Process

Yuichiro SASAKI,  Katsumi OKASHITA,  Keiichi NAKAMOTO,  Taro KITAOKA,  Bunji MIZUNO,  Mototsugu OGURA,  

[Date]2009/1/19
[Paper #]SDM2008-201
A low standby power 40nm CMOS technology

R. Watanabe,  A. Oishi,  T. Sanuki,  H. Kimijima,  K. Okamoto,  S. Fujita,  H. Fukui,  K. Yoshida,  H. Otani,  E. Morifuji,  K. Kojima,  M. Inohara,  H. Igrashi,  K. Honda,  H. Yoshimura,  T. Nakayama,  S. Miyake,  T. Hirai,  T. Iwamoto,  Y. Nakahara,  K. Kinoshita,  T. Morimoto,  S. Kobayashi,  S. Kyoh,  M. Ikeda,  K. Imai,  M. Iwai,  N. Nakamura,  F. Matsuoka,  

[Date]2009/1/19
[Paper #]SDM2008-202
Variability Analysis for Metal-Gate FinFETs Using Compact Model

S. O'uchi,  T. Matsukawa,  T. Nakagawa,  K. Endo,  Y.X. Liu,  T. Sekigawa,  J. Tsukada,  Y. Ishikawa,  H. Yamauchi,  H. Koike,  K. Sakamoto,  M. Masahara,  K. Ishii,  E. Suzuki,  

[Date]2009/1/19
[Paper #]SDM2008-203
Comprehensive Study on V_ Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation

Nobuyuki SUGII,  Ryuta TSUCHIYA,  Takashi ISHIGAKI,  Yusuke MORITA,  Hiroyuki YOSHIMOTO,  Kazuyoshi TORII,  Shin'ichiro KIMURA,  

[Date]2009/1/19
[Paper #]SDM2008-204
Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics

Toshiharu NAGUMO,  Makoto MIYAMURA,  Kiyoshi TAKEUCHI,  Koichi TAKEDA,  Masami HANE,  

[Date]2009/1/19
[Paper #]SDM2008-205
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[Date]2009/1/19
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[Date]2009/1/19
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[Date]2009/1/19
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