Electronics-Silicon Devices and Materials(Date:2008/02/01)

Presentation
表紙

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[Date]2008/2/1
[Paper #]
目次

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[Date]2008/2/1
[Paper #]
On-chip Optical Interconnect Technology

Keishi OHASHI,  

[Date]2008/2/1
[Paper #]SDM2007-263
Development of an Eco-friendly Copper Interconnect Cleaning Process

Hisashi OKUCHI,  Yoshihiro UOZUMI,  Tsuyoshi MATSUMURA,  Yasuhito YOSHIMIZU,  Takahito NAKAJIMA,  Hiroshi TOMITA,  

[Date]2008/2/1
[Paper #]SDM2007-264
32nm世代以降の高信頼多層配線に向けた超薄膜バリア技術(配線・実装技術と関連材料技術)

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[Date]2008/2/1
[Paper #]SDM2007-265
Cost-effective and High Performance Cu Interconnects (k_=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)

Makoto UEKI,  Hironori YAMAMOTO,  Fuminori ITO,  TAKEUCHI Tsuneo /,  Shinobu SAITO,  Naoya FURUTAKE,  Takahiro ONODERA,  Yoshihiro HAYASHI,  

[Date]2008/2/1
[Paper #]SDM2007-266
32nm node Ultralow-k(k=2.1)/Cu Damascene Multilevel Interconnect using High-Porosity (50%) High-Modulus (9GPa) Self-Assembled Porous Silica

S. Chikaki,  K. Kinoshita,  T. Nakayama,  K. Kohmura,  H. Tanaka,  M. Hirakawa,  E. Soda,  Y. Seino,  N. Hata,  T. Kikkawa,  S. Saito,  

[Date]2008/2/1
[Paper #]SDM2007-267
Pore-Connectivity Dependence of Moisture Absorption into Porous Low-k Films by Positron-Annihilation Lifetime Spectroscopy

Fuminori ITO,  Tsuneo TAKEUCHI,  Hironori YAMAMOTO,  Toshiyuki OHDAIRA,  Ryoichi SUZUKI,  Yoshihiro HAYASHI,  

[Date]2008/2/1
[Paper #]SDM2007-268
The TDDB Lifetime Estimation of Via-Attached Cu Lines

Hiroshi MIYAZAKI,  Daisuke KODAMA,  Naohito SUZUMURA,  

[Date]2008/2/1
[Paper #]SDM2007-269
A Study of Adhesion and Improvement of Adhesion Energy Using Hybrid Low-k (porous-PAr/ porous-SiOC(k=2.3/2.3)) Structures with Multi-layered Cu Interconnects for 45-nm Node Devices

Tatsuya USAMI,  Masayoshi TAGAMI,  Kei WATANABE,  Takatoshi KAMESHIMA,  Hideaki MASUDA,  Miyoko SHIMADA,  Akifumi GAWASE,  Yoshihisa KAGAWA,  Naofumi NAKAMURA,  Hideshi MIYAJIMA,  Hiroshi NARUSE,  Yoshiyuki ENOMOTO,  Tomohisa KITANO,  Makoto SEKINE,  

[Date]2008/2/1
[Paper #]SDM2007-270
Three-Dimensional Integration Technology Based on Wafer-on-Wafer Bonding Technique with Self-Assembly

Takafumi FUKUSHIMA,  Tetsu TANAKA,  Mitsumasa KOYANAGI,  

[Date]2008/2/1
[Paper #]SDM2007-271
Wafer-Level-Packaging Inductor with Extremely High Quality Factor and its Application to 5.8GHz LC-type Voltage Controlled Oscillator

Hideki HATAKEYAMA,  Kenichi OKADA,  Kazuma OHASHI,  Yusaku ITO,  Yusuke UEMICHI,  Naoyuki OZAWA,  Masakazu SATO,  Takuya AIZAWA,  Tatsuya ITO,  Ryozo YAMAUCHI,  Kazuya MASU,  

[Date]2008/2/1
[Paper #]SDM2007-272
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[Date]2008/2/1
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Notice for Photocopying

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[Date]2008/2/1
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奥付

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[Date]2008/2/1
[Paper #]