Electronics-Silicon Devices and Materials(Date:2008/01/17)

Presentation
表紙

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[Date]2008/1/17
[Paper #]
目次

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[Date]2008/1/17
[Paper #]
Intrinsic Mobility Reduction Mechanism in High-k Gate Dielectrics

Hiroyuki Ota,  Akito Hirano,  Yukimune Watanabe,  Naoki Yasuda,  Kunihiko Iwamoto,  Koji Akiyama,  Kenji Okada,  Shinji Migita,  Toshihide Nabatame,  Akira Toriumi,  

[Date]2008/1/17
[Paper #]SDM2007-238
Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of Less Than 4nm

Ken SHIMIZU,  Toshiro HIRAMOTO,  

[Date]2008/1/17
[Paper #]SDM2007-239
High Mobility in Ultrathin-Body Double-Gate SOI p-FET with Sub-10-nm Body Thickness : Role of Light-Hole Band and Compatibility with Uniaxial Stress Engineering

Shigeki KOBAYASHI,  Masumi SAITOH,  Ken UCHIDA,  

[Date]2008/1/17
[Paper #]SDM2007-240
High-Performance and Low-Leak Bulk Logic Platform Utilizing FET Specific Multiple Stressors with Highly Enhanced Strain for 45-nm CMOS Technology

T. Miyashita,  K. Ikeda,  Y. S. Kim,  T. Yamamoto,  Y. Sambonsugi,  H. Ochimizu,  T. Sakoda,  H. Minakata,  Y. Hayami,  K. Ookoshi,  Y. Shimamune,  M. Fukuda,  K. Okabe,  T. Kubo,  M. Tajima,  T. Yamamoto,  T. Owada,  T. Mori,  K. Sukegawa,  A. Tsukune,  K. Ikeda,  M. Kase,  T. Sugii,  

[Date]2008/1/17
[Paper #]SDM2007-241
不純物閉じ込め層(DCL)を有するサブ40nm高性能CMOS特性(<特集>IEDM(先端CMOSデバイス・プロセス技術))

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[Date]2008/1/17
[Paper #]SDM2007-242
Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

S. Mayuzumi,  J. Wang,  S. Yamakawa,  Y. Tateshita,  T. Hirano,  M. Nakata,  S. Yamaguchi,  Y. Yamamoto,  Y. Miyanami,  I. Oshiyama,  K. Tanaka,  K. Tai,  K. Ogawa,  K. Kugimiya,  Y. Nagahama,  Y. Hagimoto,  R. Yamamoto,  S. Kanda,  K. Nagano,  H. Wakabayashi,  Y. Tagawa,  M. Tsukamoto,  H. Iwamoto,  M. Saito,  S. Kadomura,  N. Nagashima,  

[Date]2008/1/17
[Paper #]SDM2007-243
Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Y. Fukuzumi,  R. Katsumata,  M. Kito,  M. Kido,  M. Sato,  H. Tanaka,  Y. Nagata,  Y. Matsuoka,  Y. Iwata,  H. Aochi,  A. Nitayama,  

[Date]2008/1/17
[Paper #]SDM2007-244
Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

Kiyoshi Takeuchi,  Toshinori Fukai,  Takaaki Tsunomura,  Arifin Tamsir Putra,  Akio Nishida,  Shiro Kamohara,  Toshiro Hiramoto,  

[Date]2008/1/17
[Paper #]SDM2007-245
Controllable Inverter Delay and Suppressing V_ Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

Ryuta Tsuchiya,  Takashi Ishigaki,  Yusuke Morita,  Masanao Yamaoka,  Toshiaki Iwamatsu,  Takashi Ipposhi,  Hidekazu Oda,  Nobuyuki Sugii,  Shin'ichiro Kimura,  Kiyoo Itoh,  Yasuo Inoue,  

[Date]2008/1/17
[Paper #]SDM2007-246
DC Characteristic Variability in FinFET SRAM Cell for 32nm node and beyond

S. Inaba,  H. Kawasaki,  K. Okano,  T. Izumida,  A. Yagishita,  A. Kaneko,  K. Ishimaru,  N. Aoki,  Y. Toyoshima,  

[Date]2008/1/17
[Paper #]SDM2007-247
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[Date]2008/1/17
[Paper #]
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[Date]2008/1/17
[Paper #]
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[Date]2008/1/17
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