Electronics-Silicon Devices and Materials(Date:2006/01/13)

Presentation
表紙

,  

[Date]2006/1/13
[Paper #]
目次

,  

[Date]2006/1/13
[Paper #]
High Performance Multi-Gate pMOSFETs using Uniaxilly-Strained SGOI Channels

T. IRISAWA,  T. NUMATA,  T. TEZUKA,  K. USUDA,  S. NAKAHARAI,  N. HIRASHITA,  N. SUGIYAMA,  E. TOYODA,  S. TAKAGI,  

[Date]2006/1/13
[Paper #]SDM2005-224
Mobility Enhancement due to Volume Inversion in (110)-oriented Ultra-thin Body Double-gate nMOSFETs with Body Thickness less than 5nm

Gen TSUTSUI,  Masumi SAITOH,  Takuya SARAYA,  Toshiharu NAGUMO,  Toshiro HIRAMOTO,  

[Date]2006/1/13
[Paper #]SDM2005-225
Improved Sub-10-nm CMOS Devices with Elevated Source/Drain Extensions by Tunneling Si-Selective-Epitaxial-Growth

Hitoshi WAKABAYASHI,  Toru TATSUMI,  Nobuyuki IKARASHI,  Makiko OSHIDA,  Hideaki KAWAMOTO,  Nobuyuki IKEZAWA,  Takeo IKEZAWA,  Toyoji YAMAMOTO,  Masami HANE,  

[Date]2006/1/13
[Paper #]SDM2005-226
Σ型SiGe-SD構造を有する超高速45nmノード・バルクCMOSデバイス(先端CMOSデバイス・プロセス技術)

,  

[Date]2006/1/13
[Paper #]SDM2005-227
High Performance CMOSFET Technology for 45nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique

A. Oishi,  O. Fujii,  T. Yokoyama,  K. Ota,  T. Sanuki,  H. Inokuma,  K. Eda,  T. Idaka,  H. Miyajima,  S. Iwasa,  H. Yamasaki,  K. Oouchi,  K. Matsuo,  H. Nagano,  T. Komoda,  Y. Okayama,  T. Matsumoto,  K. Fukasaku,  T. Shimizu,  K. Miyano,  T. Suzuki,  K. Yahashi,  A. Horiuchi,  Y. Takegawa,  K. Saki,  S. Mori,  K. Ohno,  I. Mizushima,  M. Saito,  M. Iwai,  S. Yamada,  N. Nagashima,  F. Matsuoka,  

[Date]2006/1/13
[Paper #]SDM2005-228
A Simple Approach to Optimizing Ultra-thin SiON Gate Dielectrics Independently for n- and p-MOSFETs

Shimpei Tsujikawa,  Hiroshi Umeda,  Takaaki Kawahara,  Yoji Kawasaki,  Katsuya Shiga,  Tomohiro Yamashita,  Takashi Hayashi,  Jiro Yugami,  Yoshikazu Ohno,  Masahiro Yoneda,  

[Date]2006/1/13
[Paper #]SDM2005-229
HfSiON-CMOSFET Technology for Low Standby Power Application

M. Takayanagi,  T. Watanabe,  R. Iijima,  M. Koyama,  M. Koike,  T. Ino,  Y. Kamimuta,  K. Sekine,  K. Eguchi,  A. Nishiyama,  K. Ishimaru,  

[Date]2006/1/13
[Paper #]SDM2005-230
Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces : Guiding principles for gate metal selection

K. Shiraishi,  Y. Akasaka,  S. Miyazaki,  T. Nakayama,  T. Nakaoka,  G. Nakamura,  K. Torii,  A. Ohta,  P. Ahmet,  K. Ohmori,  H. Watanabe,  T. Chikyow,  M. L. Green,  Y. Nara,  K. Yamada,  

[Date]2006/1/13
[Paper #]SDM2005-231
A Thermally-Stable Sub-0.9nm EOT TaSix/HfSiON Gate Stack with High Electron Mobility, Suitable for Gate-First Fabrication of hp45 LOP Devices

Seiji Inumiya,  Yasushi Akasaka,  Takeo Matsuki,  Fumio Ootsuka,  Kazuyoshi Torii,  Yasuo Nara,  

[Date]2006/1/13
[Paper #]SDM2005-232
Practical FinFET Design Considering GIDL for LSTP Devices

Katsuhiko TANAKA,  Kiyoshi TAKEUCHI,  Masami HANE,  

[Date]2006/1/13
[Paper #]SDM2005-233
Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10nm Fin Width and 20nm Gate Length

K. Okano,  T. Izumida,  H. Kawasaki,  A. Kaneko,  A. Yagishita,  T. Kanemura,  M. Kondo,  S. Ito,  N. Aoki,  K. Miyano,  T. Ono,  K. Yahashi,  K. Iwade,  T. Kubota,  T. Matsushita,  I. Mizushima,  S. Inaba,  K. Ishimaru,  K. Suguro,  K. Eguchi,  Y. Tsunashima,  H. Ishiuchi,  

[Date]2006/1/13
[Paper #]SDM2005-234
Technology development of 128Mb-FBC(Floating Body Cell) Memory by 90nm CMOS process

Yoshihiro MINAMI,  Tomoaki SHINO,  Atsushi SAKAMOTO,  Tomoki HIGASHI,  Naoki KUSUNOKI,  Katsuyuki FUJITA,  Kosuke HATSUDA,  Takashi OHSAWA,  Nobutoshi AOKI,  Hiroyoshi TANIMOTO,  Mutsuo MORIKADO,  Hiroomi NAKAJIMA,  Kazumi INOH,  Takeshi HAMAMOTO,  Akihiro NITAYAMA,  

[Date]2006/1/13
[Paper #]SDM2005-235
複写される方へ

,  

[Date]2006/1/13
[Paper #]
Notice about Photocopying

,  

[Date]2006/1/13
[Paper #]
奥付

,  

[Date]2006/1/13
[Paper #]