Electronics-Silicon Devices and Materials(Date:2004/08/12)

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[Date]2004/8/12
[Paper #]
目次

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[Date]2004/8/12
[Paper #]
Dynamic CAM based on One-Hot-Spot Block Code for Use in Network Router

Satoru HANZAWA,  Takeshi SAKATA,  Kazuhiko KAJIGAYA,  Riichiro TAKEMURA,  Takayuki KAWAHARA,  

[Date]2004/8/12
[Paper #]SDM2004-120,ICD2004-62
A Stacked Vertical MOS Four-Transistor SRAM Cell with 1/3 Size of a Conventional Memory Cell

Akira Kotabe,  Kenichi Osada,  Naoki Kitai,  Mio Fujioka,  Shiro Kamohara,  Masahiro Moniwa,  Sadayuki Morita,  Yoshikazu Saitoh,  

[Date]2004/8/12
[Paper #]SDM2004-121,ICD2004-63
SRAM Memory Cells using FD-SOI for Low-Power SoC

Masanao YAMAOKA,  Kenichi OSADA,  Tyuta TSUCHIYA,  Masatada HORIUCHI,  Shinichiro KIMURA,  Takayuki KAWAHARA,  

[Date]2004/8/12
[Paper #]SDM2004-122,ICD2004-64
16MB/s High-Speed Multi-Level Programming Scheme for 4Gb AG-AND Flash Memory

K. OTSUGA,  H. KURATA,  Y. SASAGO,  T. ARIGANE,  T. KAWAMURA,  T. KOBAYASHI,  Y. IKEADA,  A. SATO,  K. KOZAKAI,  S. NODA,  M. SIMIZU,  O. TSUCHIYA,  K. HURUSAWA,  

[Date]2004/8/12
[Paper #]SDM2004-123,ICD2004-65
Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator

Munetaka ASAO,  Tomohiro INOUE,  Tetsuo HIRONAKA,  Tetsushi KOIDE,  Hans JURGEN MATTAUSCH,  

[Date]2004/8/12
[Paper #]SDM2004-124,ICD2004-66
Trends of Reconfigurable Hardware

Toshinori SUEYOSHI,  

[Date]2004/8/12
[Paper #]SDM2004-125,ICD2004-67
A Pixel-Parallel Gabor Filtering LSI Based on Merged Analog/Digital Architecture

Takashi MORIE,  Jun UMEZAWA,  Atsushi IWATA,  

[Date]2004/8/12
[Paper #]SDM2004-126,ICD2004-68
High-Speed Breaking-off-Search Motion Estimation Algorithm Minimizing Number of Block Matchings and CMOS Absolute Difference Accumulators for MPEG-4 Motion Estimation

Nobuaki Kobayashi,  Tomoki Watanabe,  Tadayoshi Enomoto,  

[Date]2004/8/12
[Paper #]SDM2004-127,ICD2004-69
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors

Hideo YAMASAKI,  Masakazu YAGI,  Tadashi SHIBATA,  

[Date]2004/8/12
[Paper #]SDM2004-128,ICD2004-70
A 1.25Gbit/s CMOS Burst-Mode Optical Transceiver for Ethernet PON System

Kazuko Nishimura,  Hiroshi Kimura,  Manabu Watanabe,  Tetsuya Nagai,  Kazuhiro Nojima,  Kazumasa Gomyo,  Masato Takata,  Mitsuhiro Iwamoto,  Hiroaki Asano,  

[Date]2004/8/12
[Paper #]SDM2004-129,ICD2004-71
5-6.4Gbps 12 channel Transceiver with Pre-emphasis and Equalizer

Syunitirou Masaki,  Hirohito Higashi,  Masaya Kibune,  Satoshi Matsubara,  Takaya Chiba,  Yoshiyasu Doi,  Hisakatsu Yamaguchi,  Hideki Takauchi,  Hideki Ishida,  Kohtaroh Gotoh,  Hirotaka Tamura,  

[Date]2004/8/12
[Paper #]SDM2004-130,ICD2004-72
A 12.5Gbps Half-rate CMOS CDR Circuit For 10Gbps Network Applications

Jun TAKASOH,  Tsutomu YOSHIMURA,  Harufusa KONDOH,  Norio HIGASHISAKA,  

[Date]2004/8/12
[Paper #]SDM2004-131,ICD2004-73
Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect

Noriyuki MIURA,  Daisuke MIZOGUCHI,  Yusmeeraz Binti YUSOF,  Takayasu SAKURAI,  Tadahiro KURODA,  

[Date]2004/8/12
[Paper #]SDM2004-132,ICD2004-74
An Automatic Direction Control Scheme for Bi-directional Bus Repeaters Using Dynamic Collaborative Driving

Masahiro NOMURA,  Taku OHSAWA,  Koichi TAKEDA,  Yoetsu NAKAZAWA,  Yoshinori HIROTA,  Yasuhiko HAGIHARA,  Naoki NISHI,  

[Date]2004/8/12
[Paper #]SDM2004-133,ICD2004-75
Lowpower Bluetooth Singlechip LSI : Circuit/Architecture/System Level Power Optimizations

Mototsugu HAMADA,  Hiroki ISHIKURO,  Ken-ichi AGAWA,  Shouhei KOUSAI,  Hiroyuki KOBAYASHI,  Duc NGUYEN,  Yoshimitsu SHIMOJO,  Fumitoshi HATORI,  

[Date]2004/8/12
[Paper #]SDM2004-134,ICD2004-76
A Background Optimization Method for PLL by Measuring Phase Jitter Performance

Shiro Dosho,  Naoshi Yanagisawa,  

[Date]2004/8/12
[Paper #]SDM2004-135,ICD2004-77
A 2Gbps and 7-multiplexing CDMA Serial Receiver Chip for Highly Flexible Robot Control System

Mitsuru SHIOZAKI,  Toru MUKAI,  Masahiro ONO,  Mamoru SASAKI,  Atsushi IWATA,  

[Date]2004/8/12
[Paper #]SDM2004-136,ICD2004-78
QUASI-PARALLEL MULTI-PATH DETECTION ARCHITECTURE USING FLOATING-GATE-MOS-BASED CDMA MATCHED FILTERS

Tomoyuki NAKAYAMA,  Toshihiko YAMASAKI,  Tadashi SHIBATA,  

[Date]2004/8/12
[Paper #]SDM2004-137,ICD2004-79
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