Electronics-Silicon Devices and Materials(Date:2003/09/22)

Presentation
表紙

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[Date]2003/9/22
[Paper #]
目次

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[Date]2003/9/22
[Paper #]
Impact of Impurity Fluctuation on Transport between metal and semiconductor

Kazuya Matsuzawa,  Atsuhiro KINOSHITA,  Naoki KUSUNOKI,  Atsushi YAGISHITA,  

[Date]2003/9/22
[Paper #]VLD2003-53
Investigation of Surface Orientation and Channel Direction Effects on MOSFET Inversion Carrier Mobility

Tatsuya EZAKI,  Hidetatsu NAKAMURA,  Toyoji YAMAMOTO,  Masami HANE,  

[Date]2003/9/22
[Paper #]VLD2003-54
Gate Electrode Overlap Effects in Quasi-Ballistic MOSFETs

Hideaki TSUCHIYA,  Motoki HORINO,  Matsuto OGAWA,  Tanroku MIYOSHI,  

[Date]2003/9/22
[Paper #]VLD2003-55
Physics-Based Analytical Model of Quantum-Mechanical Electron Wave Function Penetration into Thin Dielectric Films for Capacitance Evaluation

Yasuhiko NAKAMORI,  Kenji KOMIYA,  Yasuhisa OMURA,  

[Date]2003/9/22
[Paper #]VLD2003-56
Effect of Soft Breakdown in Ultra-Thin Gate Oxides on the Circuit Operation

Shuichi MORIKAWA,  Takuji HOSOI,  Yoshinari KAMAKURA,  Kenji TANIGUCHI,  

[Date]2003/9/22
[Paper #]VLD2003-57
Analysis of Quantum Effects by Full Band Monte Carlo Simulator FALCON

Ryo Tanabe,  Yoshio Ashizawa,  Hideki Oka,  

[Date]2003/9/22
[Paper #]VLD2003-58
Problems and Solution of DSM Variability Design in 90nm Era

Hiroo Masuda,  Masaharu Yamamoto,  Shinichi Okawa,  Masakazu Aoki,  

[Date]2003/9/22
[Paper #]VLD2003-59
DAC2003 Report : Physical Design

Atsushi Kurokawa,  Tokinori Kozawa,  

[Date]2003/9/22
[Paper #]VLD2003-60
[招待論文]DAC2003報告 : 低電力技術(プロセス・デバイス・回路・シミュレーション及び一般)

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[Date]2003/9/22
[Paper #]VLD2003-61
Non-Destructive Inverse Modeling of Cu interconnect structure in 90nm Technology Node

Tatsuya KUNIKIYO,  Tetsuya WATANABE,  Toshiki KANAMOTO,  Hiroyasu ASAZATO,  Mitsutoshi SHIROTA,  Katsumi EIKYU,  Yoshihide AJIOKA,  Hiroshi MAKINO,  Kiyoshi ISHIKAWA,  Shuhei IWADE,  Yasuo INOUE,  

[Date]2003/9/22
[Paper #]VLD2003-62
Compact Modeling of a Flash Memory Cell Including Substrate-Bias-Dependent Hot-Electron Gate Current

Ken'ichiro SONODA,  Motoaki TANIZAWA,  Satoshi SHIMIZU,  Yasuhiro ARAKI,  Shinji KAWAI,  Taku OGURA,  Shin'ichi KOBAYASHI,  Kiyoshi ISHIKAWA,  Yasuo INOUE,  Norihiko KOTANI,  

[Date]2003/9/22
[Paper #]VLD2003-63
Data Number Reduction Method for Parameter Extraction and its Application

Shuhei SATOH,  Kazuo TERADA,  Mamoru TERAUCHI,  

[Date]2003/9/22
[Paper #]VLD2003-64
Floorplan Method with Abutment Constraint using S-sequence

Yohei ISHIMARU,  Keishi SAKANUSHI,  Shinsuke KOBAYASHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2003/9/22
[Paper #]VLD2003-65
Design of an Audio Signal Level Compressor Using FPGA

Takuya MUTOH,  Shugang WE,  

[Date]2003/9/22
[Paper #]VLD2003-66
奥付

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[Date]2003/9/22
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複写される方へ

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[Date]2003/9/22
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