Electronics-Silicon Devices and Materials(Date:2002/01/15)

Presentation
表紙

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[Date]2002/1/15
[Paper #]
目次

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[Date]2002/1/15
[Paper #]
High Performance 35 nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni SALICIDE

S. Inaba,  K. Okano,  S. Matsuda,  M. Fujiwara,  A. Hokazono,  K. Adachi,  K. Ohuchi,  H. Suto,  H. Fukui,  T. Shimizu,  S. Mori,  H. Oguma,  A. Murakoshi,  T. Itani,  T. Iinuma,  T. Kudo,  H. Shibata,  S. Taniguchi,  T. Matsushita,  S. Magoshi,  Y. Watanabe,  M. Takayanagi,  A. Azuma,  H. Oyamatsu,  K. Suguro,  Y. Katsumata,  Y. Toyoshima,  H. Ishiuchi,  

[Date]2002/1/15
[Paper #]2001-SDM-213
A 100nm node CMOS technology for practical SOC application

Atsuku ONO,  Katsuhiko FUKASAKU,  Tomohiro HIRAI,  Shin KOYAMA,  Mariko MAKABE,  Tomoko MATSUDA,  Michiya TAKIMOTO,  Yorinobu KUNIMUNE,  Nobuyuki IKEZAWA,  Yasuhisa YAMADA,  Fumio KOBA,  Kiyotaka IMAI,  Norio NAKAMURA,  

[Date]2002/1/15
[Paper #]2001-SDM-214
SoC CMOS Technology for Both High Reliability and High Performance

Yukio NISHIDA,  Hirokazu SAYAMA,  Kazunobu OHTA,  Hidekazu ODA,  Miki KATAYAMA,  Yasuo INOUE,  Hiroaki MORIMOTO,  Masahide INUISHI,  

[Date]2002/1/15
[Paper #]2001-SDM-215
A 50-nm CMOS Technology for High-speed, Low-Power, and RF Applications in 100-nm node SoC Platform

K. Ohnishi,  R. Tsuchiya,  T. Yamauchi,  F. Ootsuka,  K. Mitsuda,  M. Hase,  T. Nakamura,  T. Kawahara,  T. Onai,  

[Date]2002/1/15
[Paper #]2001-SDM-216
70 nm SOI-CMOS of 135 GHz f_with Dual Offset-Implanted Source-Drain Extension Structure for RF/Analog and Logic Applications

T. Matsumoto,  S. Maeda,  K. Ota,  Y. Hirano,  K. Eikyu,  H. Sayama,  T. Iwamatsu,  K. Yamamoto,  T. Katoh,  Y. Yamaguchi,  T. Ipposhi,  H. Oda,  S. Maegawa,  Y. Inoue,  M. Inuishi,  

[Date]2002/1/15
[Paper #]2001-SDM-217
Proposal of an Artificial Fingerprint Device (AFD) Module using Poly-Si Thin Film Transistors with Logic LSI Compatible Process for Built-in Security

S. Maeda,  H. Kuriyama,  T. Ipposhi,  S. Maegawa,  M. Inuishi,  

[Date]2002/1/15
[Paper #]2001-SDM-218
Novel Ultra High Density Flash Memory with A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell

Kazushi KINOSHITA,  Tetsuo ENDOH,  Takuji TANIGAMI,  Yoshihisa Wada,  Kota SATO,  Kazuya YAMADA,  Takashi YOKOYAMA,  Noboru TAKEUCHI,  Kenichi TANAKA,  Nobuyoshi AWAYA,  Keizou SAKIYAMA,  Fujio MASUOKA,  

[Date]2002/1/15
[Paper #]2001-SDM-219
Analytical model of the trap-density-dependent programming characteristics of MONOS memories and its application to a MONS memory

Kazumasa NOMOTO,  Ichiro FUJIWARA,  Hiroshi AOZASA,  Toshio TERANO,  Toshio KOBAYASHI,  

[Date]2002/1/15
[Paper #]2001-SDM-220
A 185 GHz fmax SOI DTMOS with A New Metallic Overlay-gate for Low-power RF Applications : The format of Technical Report

Tatsuya HIROSE,  Youich MOMIYAMA,  Masato KOSUGI,  Hideki KANO,  Yuu WATANABE,  Toshihiro SUGII,  

[Date]2002/1/15
[Paper #]2001-SDM-221
FD/DG-SOI MOSFET : a viable approach to overcoming the device scaling limit

Digh Hisamoto,  

[Date]2002/1/15
[Paper #]2001-SDM-222
A New Multiple Transistor Parameter Design Methodology based on a SoC Performance Evaluation Function

Kiyoshi TAKEUCHI,  Tohru MOGAMI,  

[Date]2002/1/15
[Paper #]2001-SDM-223
SON-MOSFET using ESS technique for SoC applications

Tsutomu SATO,  Hideaki NII,  Masayuki HATANO,  Keiichi TAKENAKA,  Hisataka HAYASHI,  Kazutaka ISHIGO,  Tomoyuki HIRANO,  Kazuhiko IDA,  Nobutoshi AOKI,  Tatsuya OHGURO,  Kazumi INO,  Ichiro MIZUSHIMA,  Yoshitaka TSUNASHIMA,  

[Date]2002/1/15
[Paper #]2001-SDM-224
Device Design Using Quantum Mechantical Narrow Channel Effects in Ultra-Narrow MOSFETs

Hideaki MAJIMA,  Yuta SAITO,  Toshiro HIRAMOTO,  

[Date]2002/1/15
[Paper #]2001-SDM-225
量子閉じ込め効果が薄膜SOI MOSFETの電気特性に与える影響について

Ken Uchida,  Junji Koga,  Ryuji Ohba,  Toshinori Numata,  Shin-ichi Takagi,  

[Date]2002/1/15
[Paper #]2001-SDM-226
[OTHERS]

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[Date]2002/1/15
[Paper #]