Electronics-Silicon Devices and Materials(Date:2001/07/26)

Presentation
表紙

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[Date]2001/7/26
[Paper #]
目次

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[Date]2001/7/26
[Paper #]
MPEG-4 Video Codec LSI : Its Features and Core Technology

Shun-ichi Kurohmaru,  Junji Michiyama,  

[Date]2001/7/26
[Paper #]SDM2001-113,ICD2001-36
Design of General Purpose Vision Chip with PE blocking function

Takashi Komuro,  Masatoshi Ishikawa,  

[Date]2001/7/26
[Paper #]SDM2001-114,ICD2001-37
One-Chip 15-Frame/s Mega-pixel Real-time Image Processor

Hideki YAMAUCHI,  Shigeyuki OKADA,  Kazuhiko TAKETA,  Yuh MATSUDA,  Tugio MORI,  Tsuyoshi WATANABE,  Shin'ichiro OKADA,  Yoshitaka UEDA,  Hiroki MIURA,  Akio KOBAYASHI,  Naruhito TAKADA,  Yasoo HARADA,  

[Date]2001/7/26
[Paper #]SDM2001-115,ICD2001-38
Search Area Sizes Optimization for "2-Step Improved Breaking-off-Search (2S-IBOS)" Motion Estimation Algorithm and Low-Power 0.13-μm CMOS Motion Estimators for MPEG4 Encoding

Tomomi Ei,  Akira Kotabe,  Tomochika Harada,  Tadayoshi Enomoto,  

[Date]2001/7/26
[Paper #]SDM2001-116,ICD2001-39
An image recognition LSI for smart cars implemented using a configurable processor

Yoshihisa KONDO,  

[Date]2001/7/26
[Paper #]SDM2001-117,ICD2001-40
A Pulse-Modulation Pixel-Parallel Gabor Filter Circuit for Image Feature Extraction

J. Umezawa,  S. Nishijima,  M. Miyake,  T. Morie,  M. Nagata,  A. Iwata,  

[Date]2001/7/26
[Paper #]SDM2001-118,ICD2001-41
A pixel-parallel region extraction algorithm for image recognition and implementation on FPGA

T. Nakano,  S. Hikomoto,  T. Morie,  M. Nagata,  A. Iwata,  

[Date]2001/7/26
[Paper #]SDM2001-119,ICD2001-42
High-Performance CMOS Circuits in Sub-100-nm Era : Issues and Solutions

Kazuo Yano,  Naoki Kato,  

[Date]2001/7/26
[Paper #]SDM2001-120,ICD2001-43
A Low- power SOI Adder Using Reduced Swing Charge Recycling Circuits

Atsuki Inoue,  William W. Walker,  Vojin G. Oklobdzija,  Mutsuaki Kai,  Tetsuo Izawa,  

[Date]2001/7/26
[Paper #]SDM2001-121,ICD2001-44
Dynamically Controllable DC Level Converter (DCLC) Technique to Reduce Power Dissipation, and Application to High-Speed, Low-Power Circuits

Yoshinori Oka,  Hiroaki Shikano,  Tomochika Harada,  Tadayoshi Enomoto,  

[Date]2001/7/26
[Paper #]SDM2001-122,ICD2001-45
Design Tradeoffs in Sub-100nm CMOS SoC

Masayuki MIZUNO,  

[Date]2001/7/26
[Paper #]SDM2001-123,ICD2001-46
A 0.6-V Voltage Reference Circuit Based on Σ-V_ Architecture in CMOS/SIMOX

Mamoru Ugajin,  Tsuneo Tsukahara,  

[Date]2001/7/26
[Paper #]SDM2001-124,ICD2001-47
A 0.5V Power-Supply Scheme for Low Power LSIs using Multi-Vt SOI CMOS Technology

Tsuneaki Fuse,  Atsushi Kameyama,  Masako Ohta,  

[Date]2001/7/26
[Paper #]SDM2001-125,ICD2001-48
System Memories in the Post-PC Era

Takao Watanabe,  

[Date]2001/7/26
[Paper #]SDM2001-126,ICD2001-49
A Cell Transistor Scalable Array Architecture for High-Density DRAMs

Hiroaki Nakano,  Daisaburo Takashima,  

[Date]2001/7/26
[Paper #]SDM2001-127,ICD2001-50
NV-SRAM : a Nonvolatile SRAM using Ferroelectric Capacitors

Tohru Miwa,  Junichi Yamada,  Hiroki Koike,  Takeshi Nakura,  Sota Kobayashi,  Hideo Toyoshima,  

[Date]2001/7/26
[Paper #]SDM2001-128,ICD2001-51
[OTHERS]

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[Date]2001/7/26
[Paper #]