Electronics-Silicon Devices and Materials(Date:2001/03/08)

Presentation
表紙

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[Date]2001/3/8
[Paper #]
目次

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[Date]2001/3/8
[Paper #]
Source/Drain Engineering for Sub-100 nm CMOS Using Selective Epitaxial Growth Technique

A. Hokazono,  K. Ohuchi,  K. Miyano,  I. Mizushima,  Y. Tsunashima,  Y. Toyoshima,  

[Date]2001/3/8
[Paper #]SDM2000-241
Control-Gate Voltage of a Split-Gate Flash EEPROM for Extracting the Coupling Coefficient from the Subthreshold Slope Method

H. Fujiwara,  T. Hiroshima,  M. Arimoto,  T. Kaida,  K. Honma,  S. Sudo,  K. Kurooka,  M. Hirase,  K. Mameno,  

[Date]2001/3/8
[Paper #]SDM2000-242
Low-Leakage and Highly Reliable 1.5 nm SiON Gate Dielectric Using Radical Oxynitridation for Sub-0.1 μm CMOS

Mitsuhiro Togo,  Koji Watanabe,  Toyoji Yamamoto,  Nobuyuki Ikarashi,  Tohru Tatsumi,  Haruhiko Ono,  Tohru Mogami,  

[Date]2001/3/8
[Paper #]SDM2000-03
Quantum Mechanical Narrow Channel Effect in Ultra Narrow MOSFETs

H. Majima,  T. Hiramoto,  

[Date]2001/3/8
[Paper #]SDM2000-244
Device Structure and Electrical Characteristics of Strained-Si-on-Insulator (Strained-SOI) MOSFETs

Shin-ichi Takagi,  Tomohisa Mizuno,  Naoharu Sugiyama,  Tsutomu Tezuka,  Tetsuo Hatakeyama,  Koji Usuda,  Atushi Kurobe,  

[Date]2001/3/8
[Paper #]SDM2000-245
The Influence of The Device Miniaturization on The I_ Enhancement in i-body SOI-MOSFET's

Risho Koh,  Hisashi Takemura,  Kiyoshi Takeuchi,  Tohru Mogami,  

[Date]2001/3/8
[Paper #]SDM2000-246
Suppression for Threshold Voltage Fluctuation due to SOI Thickness Variation in Fully-depleted SOI MOSFETs

Toshinori Numata,  Mitsuhiro Noguchi,  Yukihito Oowaki,  Shin-ichi Takagi,  

[Date]2001/3/8
[Paper #]SDM2000-247
Characteristic of SOI-MOSFET with Ni-silicide Schottky-Barrier Source/Drain

Gou Nakagawa,  Takayori Shikano,  Tanemasa Asano,  

[Date]2001/3/8
[Paper #]SDM2000-248
Enhancement of FD SOI MOSFET properties by the fully-silicided S/D structure

Takashi Ichimori,  Norio Hirashita,  

[Date]2001/3/8
[Paper #]SDM2000-249
C-Band SOI Power MOSFETs Fabricated Using Bonded SOI Substrate

Satoshi Matsumoto,  Yasushi Hiraoka,  Tatsuo Sakai,  

[Date]2001/3/8
[Paper #]SDM2000-250
Substrate's Potential Fixing of High Voltage SOI-IC by BOX Piercing Contact

Kenya Kobayashi,  Masayuki Itou,  Kazunari Takasugi,  Masahiro Toeda,  

[Date]2001/3/8
[Paper #]SDM2000-251
Effect of Gate Potential on Photosensing Characteristic of SOI-MOSFET/Photodiode Composite Device

Yuko Uryu,  Tanemasa Asano,  

[Date]2001/3/8
[Paper #]SDM2000-252
[OTHERS]

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[Date]2001/3/8
[Paper #]