Electronics-Silicon Devices and Materials(Date:2000/03/13)

Presentation
表紙

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[Date]2000/3/13
[Paper #]
目次

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[Date]2000/3/13
[Paper #]
Analysis and Improvement of Limited Current Drivability in Floating Partially-Depleted SOI MOSFET's

T. Matsumoto,  S. Maeda,  Y. Hirano,  Y. Yamaguchi,  S. Maegawa,  M. Inuishi,  T. Nishimura,  

[Date]2000/3/13
[Paper #]SDM99-225
Surface defects on SOI wafers and their influences on device characteristics

H. Naruoka,  N. Hattori,  T. Iwamatsu,  T. Ipposhi,  M. Sudo,  T. Nakai,  H. Yamamoto,  Y. Mashiko,  

[Date]2000/3/13
[Paper #]SDM99-226
A Lateral BJT on SOI with Low Base Resistance

T. Yamada,  H. Nii,  K. Inoh,  T. Shino,  S. Kawanaka,  Y Minami,  T. Fuse,  M. Yoshimi,  Y. Katsumata,  S. Watanabe,  J. Matsunaga,  H Ishiuchi,  

[Date]2000/3/13
[Paper #]SDM99-227
Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs(VTCMOS)and its Scalability

Hiroshi Koura,  Makoto Takamiya,  Takashi Inukai,  Toshiro Hiramoto,  

[Date]2000/3/13
[Paper #]SDM99-228
Quality evaluation of SOI materials and technological issues to be solved

Makoto Yoshimi,  Shigeto Maegawa,  Toshiaki Tsuchiya,  Mizuho Morita,  Kiyoshi Demizu,  Tadahiro Ohmi,  

[Date]2000/3/13
[Paper #]SDM99-229
Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs

Risho Koh,  Tohru Mogami,  

[Date]2000/3/13
[Paper #]SDM99-230
Control of Grain Position in Solid-Phase Crystallized Poly-Si Films by Metal Imprint Technology and Its Application to High Performance TFT

Kenji Makihira,  Tanemasa Asano,  

[Date]2000/3/13
[Paper #]SDM99-231
Mechanism of the Degradation induced by Electrical Stress in n- and p-Channel Poly-Si TFT's

Y.S. Jeong,  D. Nagashima,  H. Kuwano,  T. Nouda,  H. Hamada,  

[Date]2000/3/13
[Paper #]SDM99-232
Blockin Capability of a High- Voltage Lateral Device with Multi-Level Metal Interconnect Structure

Hitoshi Sumida,  Atsuo Hirabayashi,  

[Date]2000/3/13
[Paper #]SDM99-233
20V and 8 V Lateral Trench Gate Power MOSFETs with Record-Low On-resistance

Yusuke Kawaguchi,  Takeshi Sano,  Akio Nakagawa,  

[Date]2000/3/13
[Paper #]SDM99-234
[OTHERS]

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[Date]2000/3/13
[Paper #]