Electronics-Silicon Devices and Materials(Date:1999/06/24)

Presentation
表紙

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[Date]1999/6/24
[Paper #]
目次

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[Date]1999/6/24
[Paper #]
A Dynamically Reconfigurable Logic LSI with flexible reconfigration control mechanism

Koichiro Furuta,  Taro Fujii,  Masato Motomura,  Masahiro Nomura,  Masayuki Mizuno,  Ken-iciro Anjo,  Kazutoshi Wakabayashi,  Yoshinori Hirota,  Yo-etsu Nakazawa,  Hiroshi Ito,  Masakazu Yamashina,  

[Date]1999/6/24
[Paper #]SDM99-29
A compact 54×54-bit Multiplier with Improved Wallace-Tree Structure

Niichi Itoh,  Yuka Naemura,  Hiroshi Makino,  Yasunobu Nakase,  

[Date]1999/6/24
[Paper #]SDM99-30
Floating Point Power Calculation Unit for 3D Graphics Geometry Processing

Yoshitsugu Inoue,  Hiroyuki Kawai,  Junko Kobara,  Keijiro Yoshimatsu,  Robert Streitenberger,  Nelson Chan,  Hiroyasu Negishi,  Masatoshi Kameyama,  Kazuyasu Fujishima,  

[Date]1999/6/24
[Paper #]SDM99-31
4-bit Breaking-off-search Motion Estimation Algorithm and Low Power CMOS Absolute Difference Accumulator LSI

J. Matsumoto,  T. Oosawa,  Y. Sasajima,  T. Enomoto,  

[Date]1999/6/24
[Paper #]SDM99-32
Motion Vector Estimation Using MSB of Pixel Data and a Small, Low Power CMOS Absolute Difference Accumulator Array LSI

A. Kotabe,  T. Oosawa,  Y. Sasajima,  T. Enomoto,  

[Date]1999/6/24
[Paper #]SDM99-33
A Single-Chip MPEG2 442@ML Video, Audio and System Encoder with a 162-MHz Media-Processor and Dual Motion Estimation Cores

Kiyofumi Kawamoto,  Satoshi Kumaki,  Tetsuya Matsumura,  Kazuya Ishihara,  Hiroshi Segawa,  Hideo Ohira,  Toshiaki Shimada,  Hidenori Sato,  Takashi Hattori,  Tetsuro Wada,  Hiroshi Honma,  Tetsuya Watanabe,  Hisakazu Sato,  Ken-ichi Asano,  Toyohiko Yoshida,  

[Date]1999/6/24
[Paper #]SDM99-34
A MPEG4 Codec DSP

Takashi HASHIMOTO,  Shun-ichi KUROMARU,  Masatoshi MATSUO,  Hiromasa NAKAJIMA,  Yasuo KOHASHI,  Tomonori YONEZAWA,  Toshihiro MORI-IWA,  Masahiro OHASHI,  Masayoshi TOJIMA,  Tsuyoshi NAKAMURA,  Mana HAMADA,  Hitoshi FUJIMOTO,  Yasuo IIZUKA,  Junji MICHIYAMA,  Hiroyuki KOMORI,  

[Date]1999/6/24
[Paper #]SDM99-35
110GB/s Simultaneous Bi-directional Transceiver Logic Synchronized with a System Clock

Akira Nishida,  Tohiro Takahashi,  Takashi Muto,  Yuji Shirai,  Fumihiko Shirotori,  Yoshifumi Takada,  Akira Yamagiwa,  Atsuo Hotta,  Tadashi Kiyuna,  

[Date]1999/6/24
[Paper #]SDM99-36
A 2-Byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking

Hideki Takauchi,  Kohtaroh Gotoh,  Hirotaka Tamura,  Tsz shing Cheung,  Weixin Gai,  Yoichi Koyanagi,  Richard Schober,  Raghu Sastry,  Frank Chen,  

[Date]1999/6/24
[Paper #]SDM99-37
LSI's towards the Year 2010 and Low-Power Technology

Takayasu Sakurai,  

[Date]1999/6/24
[Paper #]SDM99-38
A prospect of future LSI technologies in IMT-2000 terminal

Susumu Uriya,  

[Date]1999/6/24
[Paper #]SDM99-39
Low-Voltage CMOS Digital Circuits : Present and Future

Hiroyuki Mizuno,  

[Date]1999/6/24
[Paper #]SDM99-40
[OTHERS]

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[Date]1999/6/24
[Paper #]