Electronics-Silicon Devices and Materials(Date:1998/07/23)

Presentation
表紙

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[Date]1998/7/23
[Paper #]
目次

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[Date]1998/7/23
[Paper #]
Analysis of MOS Capacitor Degradation Mechanism by Steady/Transient Current Separation Method

Renichi Yamada,  Jiro Yugami,  Makoto Ohkura,  

[Date]1998/7/23
[Paper #]SDM98-76,ICD98-75
Effects of buried oxide stress on thin-film silicon-on-insulator metal-oxide-semiconductor field-effect-transistor

Jong-Wook Lee,  Myung-Hee Nam,  Jeong-Hee Oh,  Ji-Woon Yang,  Won-Chang Lee,  Hyung-Ki Kim,  Min-Rok Oh,  Yo-Hwan Koh,  

[Date]1998/7/23
[Paper #]SDM98-77,ICD98-76
Scaling of delta-doped channel MOSFET with suppressed statistical Vth fluctuationsScaling of delta-doped channel MOSFET with suppressed statistical Vth fluctuations

Yuri YASUDA,  Makoto TAKAMIYA,  Toshiro HIRAMOTO,  

[Date]1998/7/23
[Paper #]SDM98-78,ICD98-77
Models and Technology of Double-Gate SOI MOSFETs

Kunihiro Suzuki,  

[Date]1998/7/23
[Paper #]SDM98-79,ICD98-78
Theoretical Study of Si Resonant Tunneling MOS Transistor

Naoto MATSUO,  Takashi MIURA,  Hiroki HAMADA,  Shinichi NAKATA,  Tadaki MIYOSHI,  

[Date]1998/7/23
[Paper #]SDM98-80,IDC98-79
A New Charge Pumping Device

In-Young Chung,  Young June Park,  Hong Shick Min,  

[Date]1998/7/23
[Paper #]SDM98-81,ICD98-80
A Model for Biomolecular Computing

Takafumi Aoki,  Masahiko Hiratsuka,  Tatsuo Higuchi,  

[Date]1998/7/23
[Paper #]SDM98-82,ICD98-81
A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current

Hiroshi Kawaguchi,  Kouichi Nose,  Takayasu Sakurai,  

[Date]1998/7/23
[Paper #]SDM98-83,ICD98-82
Low power, High Performance Megacell Circuit Technique for Sub-1V CMOS VLSI

Ilhun Son,  Daejin Myoung,  Kyung-Ah Chung,  Jeongsik Lim,  Hoonsik Cho,  

[Date]1998/7/23
[Paper #]SDM98-84,ICD98-83
A sub-1-V Triple-Threshold CMOS/SIMOX Circuit for Active Power Reduction

Koji FUJII,  Takakuni DOUSEKI,  Mitsuru HARADA,  

[Date]1998/7/23
[Paper #]SDM98-85,ICD98-84
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Mototsugu Hamada,  Masafumi Takahashi,  Hideho Arakida,  Akihiko Cgiba,  Toshihiko Terasawa,  Takashi Ishikawa,  Masahiro Kanazawa,  Mutsunori Igarashi,  Kimiyoshi Usami,  Tadahiro Kuroda,  

[Date]1998/7/23
[Paper #]SDM98-86,ICD98-85
A Non-Feedback Skew Suppression Circuit, Synchronous Mirror Delay

Takanori Saeki,  

[Date]1998/7/23
[Paper #]SDM98-87,ICD98-86
A Fast Delay Locking Circuit with Duty-Preservation

Yun-Hak Koh,  Oh-Kyong Kwon,  

[Date]1998/7/23
[Paper #]SDM98-88,ICD98-87
Electrical properties of sputtered BST thin film capacitors on in-situ oxygen-doped platinum electrodes

A. Yutani,  T. Okudaira,  Y. Tsunemine,  k. Hanafusa,  K. Kashihara,  Y. Fijita,  H. Itoh,  H. Miyoshi,  

[Date]1998/7/23
[Paper #]SDM98-89,ICD98-88
Evaluation of tailored perovskite electrode for(Ba, Sr)TiO_3

Dyun-Kyun Choi,  Se-Guen Park,  Boum Seock Kim,  Sung-Sik Park,  

[Date]1998/7/23
[Paper #]SDM98-90,ICD98-89
Back-end Integration of Pt/BST/Pt Capacitor for ULSI DRAM Applications

Ki Hoon Lee,  Byoung Taek Lee,  Wan Don Kim,  Suk Ho Joo,  Hideki Horii,  Hong Bae Park,  Chang Seok Kang,  Han Jin Lim,  Cha-Young Yoo,  Sang In Lee,  Moon Young Lee,  

[Date]1998/7/23
[Paper #]SDM98-91,ICD98-90
[OTHERS]

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[Date]1998/7/23
[Paper #]