Electronics-Silicon Devices and Materials(Date:1998/06/19)

Presentation
表紙

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[Date]1998/6/19
[Paper #]
目次

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[Date]1998/6/19
[Paper #]
Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's

Hiroshi Kawaguchi,  Yasuhito Itaka,  Takayasu Sakurai,  

[Date]1998/6/19
[Paper #]ED98-62,SDM98-62,ICD98-61
A high density VIA2 ROM development for Digital Signal Processor

Shigetoshi Muramatsu,  Masayasu Itoigawa,  Hiroshi Takahashi,  

[Date]1998/6/19
[Paper #]ED98-63,SDM98-63,ICD98-62
A 5.3GB/s embedded SDRAM core with slightly boosting scheme

H Noda,  A Yamazaki,  T Yamagata,  I Hayashi,  K Arimoto,  M Yamada,  

[Date]1998/6/19
[Paper #]ED98-64,SDM98-64,ICD98-63
A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories

Tsutomu Yoshimura,  Yasunobu Nakase,  Naoya Watanabe,  Yoshikazu Morooka,  Masahiko Hyozo,  Yoshio Matsuda,  Masaki Kumanoya,  

[Date]1998/6/19
[Paper #]ED98-65,SDM98-65,ICD98-64
An On-chip Timing Adjuster with Sub-100-ps Resolution for a High-Speed DRAM Interface

Hiromasa Noda,  Masakazu Aoki,  Hitoshi Tanaka,  Osamu Nagashima,  Hideyuki Aoki,  

[Date]1998/6/19
[Paper #]ED98-66,SDM98-66,ICD98-65
5GByte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM

Takashi Sato,  Yoji Nishio,  Toshio Sugano,  Yoshinobu Nakagome,  

[Date]1998/6/19
[Paper #]ED98-67,SDM98-67,ICD98-66
A 4.25Gb/s CMOS Fiber Channel Transceiver LSI

Muneo Fukaishi,  Kazuyuki Nakamura,  Masaharu Sato,  Yutaka Tsutsui,  Syuji Kishi,  Michio Yotsuyanagi,  

[Date]1998/6/19
[Paper #]ED98-68,SDM98-68,ICD98-67
A High Speed and Low Power GaAs Delay Flip-Flop

H Satoh,  T Enomoto,  A Hirobe,  T Iwata,  M Oh-hashi,  M Fujii,  N Yoshida,  S Asai,  

[Date]1998/6/19
[Paper #]ED98-69,SDM98-69,ICD98-68
40-GHz frequency dividers with reduced power dissipation fabricated using high-speed, small-emitter-area AlGaAs/InGaAs HBTs

Yasushi Amamiya,  Takaki Niwa,  Nobuo Nagano,  Masayuki Mamada,  Yasuyuki Suzuki,  Hidenori Shimawaki,  

[Date]1998/6/19
[Paper #]ED98-70,SDM98-70,ICD98-69
Design of Low-Power CMOS Cell Library

Yutaka MURATA,  Ken'ichiro UDA,  Bu-Yeol LEE,  Kazuo TAKI,  Tsuyoshi MIZOGUCHI,  

[Date]1998/6/19
[Paper #]ED98-71,SDM98-71,ICD98-70
A sub-0.1um circuit design with substrate-over-biasing

Shigeyoshi Watanabe,  Yukihito Oowaki,  Mitsuhiro Noguchi,  Tuneaki Fuse,  Kazumasa Sunouchi,  Hitomi Kawaguchiya,  

[Date]1998/6/19
[Paper #]ED98-72,SDM98-72,ICD98-71
Design of Threshold Voltage for Ultra-Low-Voltage CMOS Circuits

Toshishige SHIMAMURA,  Takakuni DOUSEKI,  

[Date]1998/6/19
[Paper #]ED98-73,SDM98-73,ICD98-72
PLT(Partial Low Threshold)-CMOS scheme for low power applications

Shoichiro Kashiwakura,  Tetsuyoshi Shiota,  Wataru Shibamoto,  Atsuki Inoue,  Ryoichi Ohe,  Yusuke Matsunaga,  

[Date]1998/6/19
[Paper #]ED98-74,SDM98-74,ICD98-73
A Virtual Power/Ground Rails Clamp Scheme for Low Vt CMOS Circuits

Kouichi Kumagai,  Hiroaki Iwaki,  Hiroshi Yoshida,  Hisamitsu Suzuki,  Takashi Yamada,  Susumu Kurosawa,  

[Date]1998/6/19
[Paper #]ED98-75,SDM98-75,ICD98-74
[OTHERS]

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[Date]1998/6/19
[Paper #]