Electronics-Silicon Devices and Materials(Date:1997/03/14)

Presentation
表紙

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[Date]1997/3/14
[Paper #]
目次

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[Date]1997/3/14
[Paper #]
Experimental Verification of Large Current Capability of Lateral IEGTs on SOI

Norio Yasuhara,  Hideyuki Funaki,  Tomoko Matsudai,  Akio Nakagawa,  

[Date]1997/3/14
[Paper #]SDM96-228
Multi-Channel Lateral IGBTs on SOI

Hideyuki Funaki,  Norio Yasuhara,  Tomoko Matsudai,  Akio Nakagawa,  

[Date]1997/3/14
[Paper #]SDM96-229
New High Voltage SOI Device Structure Using SIPOS Film

Yoshihiro Yamaguchi,  Norio Yasuhara,  Keizo Hirayama,  Hideyuki Funaki,  Akio Nakagawa,  

[Date]1997/3/14
[Paper #]SDM96-230
Substrate Bias Effect on the Blocking Capability of a Lateral P-channel MOSFET on SOI

Hitoshi Sumida,  Atsuo Hirabayashi,  

[Date]1997/3/14
[Paper #]SDM96-231
Design Guidelines of Fully-Depleted SOI MOSFET's by Using Tantalum as Gate Material

Mo-Chiun Yu,  Takeo Ushiki,  Mizuho Morita,  Tadahiro Ohmi,  

[Date]1997/3/14
[Paper #]SDM96-232
A Quasi-SOI Power MOSFET Fabricated by Reversed Silicon Wafer Direct Bonding

Satoshi Matsumoto,  Toshiaki Yachi,  Hiroshi Horie,  Yoshihiro Arimoto,  

[Date]1997/3/14
[Paper #]SDM96-233
A 0.35μm Shallow SIMOX/CMOS Technology for Low-Power, High-Speed Applications

T. Naka,  A. O. Adan,  S. Kaneko,  A. Kagisawa,  

[Date]1997/3/14
[Paper #]SDM96-234
Suppression of Threshold Voltage Variation in Low-Voltage MTCMOS/SIMOX Circuit

Mitsuru Harada,  Takakuni Douseki,  Toshiaki Tsuchiya,  

[Date]1997/3/14
[Paper #]SDM96-235
Fully Depleted (FD) MOSFETs Engineering for a Shallow SIMOX/CMOS Technology

Seiji KANEKO,  Toshio NAKA,  Alberto O. ADAN,  Atsushi KAGISAWA,  

[Date]1997/3/14
[Paper #]SDM96-236
[OTHERS]

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[Date]1997/3/14
[Paper #]