Electronics-Silicon Devices and Materials(Date:1996/03/11)

Presentation
表紙

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[Date]1996/3/11
[Paper #]
目次

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[Date]1996/3/11
[Paper #]
Investigation of the parasitic MOSFET in SOI MOSFET using three-dimensional device simulation

T. Iwamatsu,  S. Miyamoto,  Y. Yamaguchi,  T. Ipposhi,  Y. Inoue,  H. Miyoshi,  

[Date]1996/3/11
[Paper #]SDM95-263
Numerical Predictions of the Lateral Insulated Gate Bipolar Transistors Formed on Quasi-SOI Substrate

S. Matsumoto,  T. Yachi,  

[Date]1996/3/11
[Paper #]SDM95-264
A 0.3μm ECL-CMOS Process Technology on SOI for Mainframe Computers

T. Kikuchi,  Y. Onishi,  T. Hashimoto,  E. Yoshida,  H. Yamaguchi,  S. Wada,  N. Tamba,  K. Watanabe,  Y. Tamaki,  T. Ikeda,  

[Date]1996/3/11
[Paper #]SDM95-265
Effect of Tungsten-Deposited Source/Drain on Suppression of Parasitic Bipolar Effects in Ultrathin-Film MOSFETs/SIMOX

Yasuhiro Sato,  Terukazu Ohno,  Toshiaki Tsuchiya,  Toshihiko Kosugi,  Hiromu Ishii,  

[Date]1996/3/11
[Paper #]SDM95-266
Threshold Voltage Control by Using Ta as Gate Material in SOI MOSFETs

Yuichi Hirano,  Hisayuki Shimada,  Takeo Ushiki,  Tadahiro Ohmi,  

[Date]1996/3/11
[Paper #]SDM95-267
Development of Sub-Quarter-μm MONOS Type Memory Transistor : Effect of Rapid Thermal Anneal on Bottom SiO_2

Machio Yamagishi,  Akihiro Nakamura,  Hiroshi Aozasa,  Yasutoshi Komatsu,  

[Date]1996/3/11
[Paper #]SDM95-268
Comparison on the short channel effect between the fully depleted and partially depleted SOI-MOSFET, using capacitance network model

R. Koh,  H. Matsumoto,  

[Date]1996/3/11
[Paper #]SDM95-269
High Voltage 60V SOI DMOSFET

Yusuke Kawaguchi,  Hideyuki Funaki,  Yoshihiro Yamaguchi,  Yoshinori Terazaki,  Akio Nakagawa,  

[Date]1996/3/11
[Paper #]SMD95-270
Electrical characteristics of germanium implanted poly-Si films

Takayuki Matsui,  Myeon-Koo Kang,  Keiji Wada,  Hiroshi Kuwano,  

[Date]1996/3/11
[Paper #]SDM95-271
Thin-SOI Process Using an Etch-stop Layer as an Active Layer

Hideyuki Unno,  Kazuo Imai,  

[Date]1996/3/11
[Paper #]SDM95-272
Thinning of SOI bonded wafers by etch stop with applying voltage.

Atsushi Ogura,  

[Date]1996/3/11
[Paper #]SDM
Possible Causes of Trace Metallic Contaminants in SIMOX Substrates

Kaori Watanabe,  Akira Yoshino,  Kensuke Okonogi,  Hiroshi Kitajima,  

[Date]1996/3/11
[Paper #]SDM95-274
Analysis of Metallic Impurities in SIMOX Wafers

J. Kodate,  K. Machida,  K. Imai,  M. Tanaka,  N. Yabumoto,  

[Date]1996/3/11
[Paper #]SDM95-275
[OTHERS]

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[Date]1996/3/11
[Paper #]