Electronics-Silicon Devices and Materials(Date:1995/11/21)

Presentation
表紙

,  

[Date]1995/11/21
[Paper #]
目次

,  

[Date]1995/11/21
[Paper #]
A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs

Satoshi UTSUGI,  Isao NARITAKE,  Tadahiko SUGIBAYASHI,  Tatsunori MUROTANI,  

[Date]1995/11/21
[Paper #]SDM95-155
Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAMs

Takeshi Hamamoto,  Yoshikazu Morooka,  Mikio Asakura,  Hideyuki Ozaki,  

[Date]1995/11/21
[Paper #]SDM95-156
A Controller Integrated 16M CDRAM with Direct Interface to CPU

Naoya Watanabe,  Katsumi Dosaka,  Akira Yamazaki,  Hideaki Abe,  Jun Ohtani,  Toshiyuki Ogawa,  Kazunori Ishihara,  Masaki Kumanoya,  

[Date]1995/11/21
[Paper #]SDM95-157
1/4 Vcc Bit-Line Swing Scheme for a 1V 4Gb DRAM

T. Inaba,  D. Takashima,  T. Ozaki,  Y. Oowaki,  S. Watanabe,  K. Ohuchi,  

[Date]1995/11/21
[Paper #]SDM95-158
A 0.9ns-1.15Mb ECL-CMOS SRAM with 30ps-120k Gates

K. Yamaguchi,  K. Higeta,  M. Usami,  M. Ohhayashi,  H. Nanbu,  

[Date]1995/11/21
[Paper #]SDM95-159
Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology

Takakuni DOUSEKI,  Shin'ichro MUTOH,  Takemi UEKI,  Junzo YAMADA,  

[Date]1995/11/21
[Paper #]SDM95-160
A Low-power Synchronous SRAM Macrocell with Column-address Controlled Virtual-GND lines

Nobutaro SHIBATA,  Mayumi WATANABE,  

[Date]1995/11/21
[Paper #]SDM95-161
A 250-622MHz Deskewing Clock Buffer using Two-Loop Architecture

Satoru Tanoi,  Tetsuya Tanabe,  Kazuhiko Takahashi,  Sanpei Miyamoto,  Masaru Uesugi,  

[Date]1995/11/21
[Paper #]SDM95-162
[OTHERS]

,  

[Date]1995/11/21
[Paper #]