Electronics-Silicon Devices and Materials(Date:1993/11/26)

Presentation
表紙

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[Date]1993/11/26
[Paper #]
目次

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[Date]1993/11/26
[Paper #]
Efficient Test Scheme for Embedded Multi-port RAMs

Tsuneo Matsumura,  Nobutaro Shibata,  Tatsuo Baba,  

[Date]1993/11/26
[Paper #]SDM93-140,ICD93-134
A 4.4Mbit Triple Port VRAM for Mlutimedia

Tetsuyuki Fukushima,  Akifumi Kawahara,  Ryoutaro Azuma,  Kazuyosi Nishi,  Akihiro Matsumoto,  Katsumi Wada,  Tomonori Kataoka,  Toshiki Mori,  

[Date]1993/11/26
[Paper #]SDM93-141,ICD93-135
250Mbyte/sec Synchronous DRAM using a 3-Stage-pipelined Architecture

Yasuhiro Takai,  Mamoru Nagase,  Mamoru Kitamura,  Yasuji Koshikawa,  Naoyuki Yoshida,  Yasuaki Kobayashi,  Takashi Obara,  Yukio Fukuzou,  Hiroshi Watanabe,  

[Date]1993/11/26
[Paper #]SDM93-142,ICD93-136
3Mbit Field Memory

Terumi Hiraoka,  Shigemi Yoshioka,  Atsushi Takasugi,  

[Date]1993/11/26
[Paper #]SDM93-143,ICD93-137
Developed MUSE memory with Modnle methodology

Kiyoshi Nakatsuka,  Isamu Nakajima,  Keisuke Takeo,  Hiroaki Tajima,  Tadashi Tachibana,  Norihisa Kitagawa,  

[Date]1993/11/26
[Paper #]SDM93-144,ICD93-138
Design of a Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor

Kazutoshi Kobayashi,  Hideki Takemura,  Wasarin Jungurradee,  Hidetoshi Onodera,  Keikichi Tamaru,  

[Date]1993/11/26
[Paper #]SDM93-145,ICD93-139
New Memory LSI′s with Very High Data Transfer Speed Using Optical Interconnection

Mitsumasa Koyanagi,  Reiji Abara,  Kohji Miyake,  Shin Yokoyama,  

[Date]1993/11/26
[Paper #]SDM93-146,ICD93-140
Two-dimensional power-line selection scheme for low subthreshold- current multi-gigabit DRAMs

Takeshi Sakata,  Masashi Horiguchi,  Masakazu Aoki,  Kiyoo Itoh,  

[Date]1993/11/26
[Paper #]SDM93-147,ICD93-141
High density Full CMOS SRAM cell utilizing shallow well design

Hiroshi Gojohbori,  Kazunari Ishimaru,  Hidetoshi Koike,  Yukari Unno,  Manabu Sai,  Fumitomo Matsuoka,  Masakazu Kakumu,  

[Date]1993/11/26
[Paper #]SDM93-148,ICD93-142
High-Speed,small-amplitude interface circuits for memory bus application

Masao Taguchi,  Satoshi Eto,  Yoshihiro Takemae,  Seiichi Saitoh,  Noriyuki Matsui,  Shigeru Takamura,  Tatsuo Koizumi,  

[Date]1993/11/26
[Paper #]SDM93-149,ICD93-143
64K×16/18bit 3.3v Bi-CMOS Fast SRAM

Kenji Kondou,  Tosio Komuro,  Masakazu Soeda,  Yasusi Yamasaki,  Hiroyuki Takahashi,  Sintaroh Asano,  Keita Maeda,  Keniti Etigoya,  Tamotu Watarai,  Minoru Yamagami,  

[Date]1993/11/26
[Paper #]SDM93-150,ICD93-144
1-Mbit BiCMOS TTL SRAM with Low Voltage and High Speed oriented Technique

Toshihiko Hirose,  Shigeki Ohbayashi,  Yoshiyuki Fujino,  Takashi Hayasaka,  Akira Hosogane,  Yoshiyuki Ishigaki,  Hirotada Kuriyama,  Yukio Maki,  Hiroki Honda,  Yasumasa Nishimura,  

[Date]1993/11/26
[Paper #]SDM93-151,ICD93-145
A 12.5ns 16Mb CMOS SRAM

Koichiro Ishibashi,  Kunihiro Komiyaji,  Sadayuki Morita,  Toshiro Aoto,  Shuji Ikeda,  Kyoichiro Asayama,  Naotaka Hashimoto,  

[Date]1993/11/26
[Paper #]SDM93-152,ICD93-146
[OTHERS]

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[Date]1993/11/26
[Paper #]