Electronics-Integrated Circuits and Devices(Date:2021/12/01)

Presentation
MTJ-based non-volatile SRAM circuit with data-aware store control for energy saving

Hisato Miyauchi(SIT),  Kimiyoshi Usami(SIT),  

[Date]2021-12-01
[Paper #]VLD2021-19,ICD2021-29,DC2021-25,RECONF2021-27
Soft Errors on Flip-flops Depending on Circuit and Layout Structures Estimated by TCAD Simulations

Moeka Kotani(KIT),  Ryuichi Nakajima(KIT),  Kazuya Ioki(ROHM),  Jun Furuta(KIT),  Kazutoshi Kobayashi(KIT),  

[Date]2021-12-01
[Paper #]VLD2021-17,ICD2021-27,DC2021-23,RECONF2021-25
Block Sparse MLP-based Vision DNN Accelerators on Embedded FPGAs

Akira Jinguji(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  

[Date]2021-12-01
[Paper #]VLD2021-21,ICD2021-31,DC2021-27,RECONF2021-29
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops

Aika Kamei(Keio Univ.),  Takuya Kojima(Keio Univ.),  Hideharu Amano(Keio Univ.),  Daiki Yokoyama(SIT),  Hisato Miyauchi(SIT),  Kimiyoshi Usami(SIT),  Keizo Hiraga(SSS),  Kenta Suzuki(SSS),  

[Date]2021-12-01
[Paper #]VLD2021-20,ICD2021-30,DC2021-26,RECONF2021-28
Triple-Rail Stochastic Number and Its Applications

Shoki Kawaminami(Ritsumeikan Univ),  Shigeru Yamashita(Ritsumeikan Univ),  

[Date]2021-12-01
[Paper #]VLD2021-26,ICD2021-36,DC2021-32,RECONF2021-34
Improving Accuracy of Addition for Stochastic Computing

Ichilawa Katsuhiro(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-27,ICD2021-37,DC2021-33,RECONF2021-35
Error Recovery Method by Canceling Errors on DMFBs

Yuji Wada(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-28,ICD2021-38,DC2021-34,RECONF2021-36
Determining Optimal Number of Layers for Network-Flow-based Sample Preparation

Akira Ishida(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-29,ICD2021-39,DC2021-35,RECONF2021-37
Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices

Kenji Mii(Osaka Univ.),  Daisuke Kanemoto(Osaka Univ.),  Osamu Maida(Osaka Univ.),  Tetsuya Hirose(Osaka Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-18,ICD2021-28,DC2021-24,RECONF2021-26
A Dual-mode SAR ADC to Detect Power Analysis Attack

Takuya Wadatsumi(Kobe Univ.),  Takuji Miki(Kobe Univ.),  Makoto Nagata(Kobe Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-30,ICD2021-40,DC2021-36,RECONF2021-38
Sparsity-Gradient-Based Pruning and the Vitis-AI Implementation for Compacting Deep Learning Models

Hengyi Li(Ritsumeikan Univ.),  Xuebin Yue(Ritsumeikan Univ.),  Lin Meng(Ritsumeikan Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-22,ICD2021-32,DC2021-28,RECONF2021-30
Examination of model validation of interlocking connection using UPPAAL

Takumi Hasegawa(Kyosan Mfg),  Kohei Yabuki(Kyosan Mfg),  Takahiro Shimura(Kyosan Mfg),  Takeshi Mizuma(UTokyo),  

[Date]2021-12-01
[Paper #]
A Multilayer Perceptron Training Accelerator using Systolic Array

Takeshi Senoo(Toyko Tech),  Akira Jinguji(Toyko Tech),  Ryosuke Kuramochi(Toyko Tech),  Hiroki Nakahara(Toyko Tech),  

[Date]2021-12-01
[Paper #]VLD2021-23,ICD2021-33,DC2021-29,RECONF2021-31
Basic evaluation of ReNA, a DNN accelerator using numerical representation posit

Yasuhiro Nakahara(Kumamoto Univ.),  Yuta Masuda(Kumamoto Univ.),  Masato Kiyama(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-24,ICD2021-34,DC2021-30,RECONF2021-32
Low power neural network by reducing the operating voltage of SRAM

Keisuke Kozu(Chiba Univ.),  Kazuteru Namba(Chiba Univ.),  

[Date]2021-12-01
[Paper #]VLD2021-25,ICD2021-35,DC2021-31,RECONF2021-33
Diagnosis of Switching-Induced IR Drop by On-Chip Voltage Monitors

Kazuki(Kobe Univ.),  Leonidas Kataselas(Aristotle Univ.),  Ferenc Fodor(IMEC),  Alkis Hatzopoulos(Aristotle Univ.),  Makoto Nagata(Kobe Univ.),  Erik Jan Marinissen(IMEC),  

[Date]2021-12-01
[Paper #]VLD2021-31,ICD2021-41,DC2021-37,RECONF2021-39
Transition of R & D themes in Design Gaia

Tadashi Okabe(TIRI),  

[Date]2021-12-02
[Paper #]VLD2021-39,ICD2021-49,DC2021-45,RECONF2021-47
Development of Spiking Neural Network with Mem Capacitor

Atsushi Sawada(NAIST),  Reon Oshio(NAIST),  Mutsumi Kimura(NAIST),  Renyuan Zhang(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2021-12-02
[Paper #]VLD2021-32,ICD2021-42,DC2021-38,RECONF2021-40
Wafer-level Variation Modeling for Multi-site Testing of RF Circuits

Riaz-ul-haque Mian(Shimane Univ.),  Michihiro Shintani(NAIST),  

[Date]2021-12-02
[Paper #]VLD2021-42,ICD2021-52,DC2021-48,RECONF2021-50
The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System

Tomoki Shimizu(Keio Univ.),  Kohei Ito(Keio Univ.),  Kensuke Iizuka(Keio Univ.),  Kazuei Hironaka(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2021-12-02
[Paper #]VLD2021-36,ICD2021-46,DC2021-42,RECONF2021-44
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