Electronics-Integrated Circuits and Devices(Date:2019/11/13)

Presentation
A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults

Peikun Wang(The Univ. of Tokyo),  Amir Masaud Gharehbaghi(The Univ. of Tokyo),  Masahiro Fujita(The Univ. of Tokyo),  

[Date]2019-11-13
[Paper #]VLD2019-32,DC2019-56
CGRAのためのアプリケーションマッピングフレームワークGenMapの実装と実機評価

Takuya Kojima(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2019-11-13
[Paper #]VLD2019-29,DC2019-53
On-Chip Leakage Monitor based Temperature Sensor Circuit for Ultra Low Voltage

Daisuke Sato(SIT),  Kimiyoshi Usami(SIT),  

[Date]2019-11-13
[Paper #]VLD2019-33,DC2019-57
Gate Level Netlist Function Classification Method Based on R-GCN

Yuichiro Fujishiro(Kumamoto Univ.),  Hiroki Oyama(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Hiroaki Yasuda(MITSUBISHI ELECTRIC ENGINEERING),  Hiroto Ito(MITSUBISHI ELECTRIC ENGINEERING),  

[Date]2019-11-13
[Paper #]VLD2019-30,DC2019-54
Improvement of variational autoencoder based test escape detection through image conversion

Romain Chicoix(Telecom SudParis),  Michihiro Shintani(NAIST),  Kouichi Kumaki(Renesas Electronics),  Michiko Inoue(NAIST),  

[Date]2019-11-13
[Paper #]VLD2019-31,DC2019-55
Design of Reference-free CMOS Temperature Sensor with Statistical MOSFET Selection

Shogo Harada(Kyoto Univ.),  Mahfuzul Islam(Kyoto Univ.),  Takashi Hisakado(Kyoto Univ.),  Osami Wada(Kyoto Univ.),  

[Date]2019-11-13
[Paper #]VLD2019-34,DC2019-58
A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs

Yuta Ishiyama(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Yuki Ikegaya(Nihon Univ.),  

[Date]2019-11-14
[Paper #]VLD2019-43,DC2019-67
Neural Network-based Lifetime Prediction and Reliability Enhancement Techniques for 3D NAND Flash Memory

Masaki Abe(Chuo Univ.),  Ken Takeuchi(Chuo Univ.),  

[Date]2019-11-14
[Paper #]ICD2019-30,IE2019-36
Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits

Koki Kamimura(Chuo Univ.),  Susumu Nohmi(Chuo Univ.),  Ken Takeuchi(Chuo Univ.),  

[Date]2019-11-14
[Paper #]ICD2019-31,IE2019-37
FPGA implementation of ISA-based sparse CNN using Wide-SIMD

Akira Jinguji(Titech),  Shimpei Sato(Titech),  Hiroki Nakahara(Titech),  

[Date]2019-11-14
[Paper #]RECONF2019-37
High-radix CORDIC algorithm for arcsine and arccosine calculation.

Hiroshi Matsuoka(Kyoto Univ.),  Naofumi Takagi(Kyoto Univ.),  

[Date]2019-11-14
[Paper #]VLD2019-42,DC2019-66
A Study of Action Recognition Method using Pose Data toward Distributed Processing over Edge and Cloud

Chikako Takasaki(Ocha Univ.),  Atsuko Takefusa(NII),  Hidemoto Nakada(AIST),  Masato Oguchi(Ocha Univ.),  

[Date]2019-11-14
[Paper #]CPSY2019-43
Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths

Suguru Rikino(Oita Univ.),  Yushiro Hiramoto(Oita Univ.),  Satoshi Ohtake(Oita Univ.),  

[Date]2019-11-14
[Paper #]VLD2019-46,DC2019-70
Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults

Yuta Nakano(Oita Univ.),  Satoshi Ohtake(Oita Univ.),  

[Date]2019-11-14
[Paper #]VLD2019-44,DC2019-68
NBTI Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement

Takumi Hosaka(Saitama Univ.),  Shinichi Nishizawa(Fukuoka Univ.),  RYO Kishida(Tokyo Univ. of Science),  Takashi Matsumoto(The Univ. of Tokyo),  Kazutoshi Kobayashi(Kyoto Institute of Tech.),  

[Date]2019-11-14
[Paper #]VLD2019-35,DC2019-59
Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method

Norihiro Nakaoka(Ehime Univ.),  Tomoki Aono(Ehime Univ.),  Sohshi Kudoh(Ehime Univ.),  Senling Wang(Ehime Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  Hiroyuki Iwata(Renesas),  Yoichi Maeda(Renesas),  Jun Matsushima(Renesas),  

[Date]2019-11-14
[Paper #]VLD2019-45,DC2019-69
FPGAによる短波海洋レーダの実現に向けた検討

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[Date]2019-11-14
[Paper #]RECONF2019-36
イジングモデルによる類似誘導部分グラフ同型問題の解法

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[Date]2019-11-14
[Paper #]VLD2019-41,DC2019-65
Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks

Tomoki Chiba(Tohoku Univ.),  Masanori Natsui(Tohoku Univ.),  Takahiro Hanyu(Tohoku Univ.),  

[Date]2019-11-14
[Paper #]ICD2019-32,IE2019-38
Domain Knowledge-aware Machine Learning System with Rule-based Guiding

Tomoaki Shikina(TAT),  Daichi Teruya(TAT),  Hironori Nakajo(TAT),  

[Date]2019-11-14
[Paper #]CPSY2019-44
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