Electronics-Integrated Circuits and Devices(Date:2017/11/06)

Presentation
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation

Shun Takeda(Nihon Univ),  Toshinori Hosokawa(Nihon Univ),  Hiroshi Yamazaki(Nihon Univ),  Masayoshi Yoshimura(Kyoto Sangyo Univ),  

[Date]2017-11-06
[Paper #]VLD2017-37,DC2017-43
An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores

Hashidate Hidemi(Nihon Univ.),  Hosokawa Toshinori(Nihon Univ.),  Yoshimura Masayoshi(Kyoto Sangyo Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-31,DC2017-37
hCODE 2.0: An Open-source Platform for FPGA Cluster System

Hiroki Nakagawa(Kumamoto Univ.),  Qian Zhao(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-27,DC2017-33
An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction

Daichi Yuruki(Oita Univ),  Satoshi Ohtake(Oita Univ),  Yoshiyuki Nakamura(Renesas Electronics),  

[Date]2017-11-06
[Paper #]VLD2017-36,DC2017-42
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis

Saya Ohira(Nihon Univ.),  Naoki Tsuchiya(Nihon Univ.),  Tetsuya Matsumura(Nihon Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-28,DC2017-34
Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure

Yasuhiro Ogasahara(AIST),  Toshihiro Sekigawa(AIST),  Hanpei Koike(AIST),  

[Date]2017-11-06
[Paper #]VLD2017-32,DC2017-38
[Invited Talk] Superconducting quantum computing

Yasunobu Nakamura(UTokyo),  

[Date]2017-11-06
[Paper #]CPM2017-79,ICD2017-38,IE2017-64
Hardware Implementation of Elliptic Curve Cryptography for Sensor-Node Applications

Ryosuke Saito(The Univ. of Tokyo),  Hiromitsu Awano(The Univ. of Tokyo),  Makoto Ikeda(The Univ. of Tokyo),  

[Date]2017-11-06
[Paper #]
FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving

Masahiro Fukuda(JAIST),  Yasushi Inoguchi(JAIST),  

[Date]2017-11-06
[Paper #]RECONF2017-37
FPGAを用いたグラフストリーム処理の一検討

Takayuki Matsuzaki(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2017-11-06
[Paper #]RECONF2017-38
Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves

Tadayuki Ichihashi(Tokyo Univ.),  Hiromitsu Awano(Tokyo Univ.),  Makoto Ikeda(Tokyo Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-30,DC2017-36
A shared memory chip for twin-tower of chips

Sayaka Terashima(Keio Univ.),  Takuya Kojima(Keio Univ.),  Hayate Okuhara(Keio Univ.),  Yusuke Matsushita(Keio Univ.),  Naoki Ando(Keio Univ.),  Mitaro Namiki(Tokyo Univ. of Agriculture and Tech.),  Hideharu Amano(Keio Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-34,DC2017-40
Considerations of Inside Structures for Approximate Multipliers

Masahiro Inoue(Fukuoka Univ.),  Kaori Tajima(Fukuoka Univ.),  Hiroyuki Baba(Fukuoka Univ.),  Tongxin Yang(Fukuoka Univ.),  Tomoaki Ukezono(Fukuoka Univ.),  Toshinori Sato(Fukuoka Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-29,DC2017-35
高周波信号からの高精度なピーク値推定システムのFPGA実装

Ryo Kamasaka(Nagasaki Univ.),  Taisei Segawa(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  

[Date]2017-11-06
[Paper #]RECONF2017-39
Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control

Yusuke Yoshida(SIT),  Kimiyoshi Usami(SIT),  

[Date]2017-11-06
[Paper #]VLD2017-33,DC2017-39
A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST

Kyonosuke Watanabe(Oita Univ.),  Satoshi Ohtake(Oita Univ.),  

[Date]2017-11-06
[Paper #]VLD2017-35,DC2017-41
[Invited Talk] Researchs on high-speed and efficient Deep Learning technologies

Takuya Fukagai(Fujitsu Lab. Ltd.),  Koichi Shirahata(Fujitsu Lab. Ltd.),  Yasumoto Tomita(Fujitsu Lab. Ltd.),  Tetsutaro Hashimoto(Fujitsu Lab. Ltd.),  Atsushi Ike(Fujitsu Lab. Ltd.),  Masafumi Yamazaki(Fujitsu Lab. Ltd.),  Akihiko Kasagi(Fujitsu Lab. Ltd.),  Tsuguchika Tabaru(Fujitsu Lab. Ltd.),  Liuan Wang(FRDC),  Song Wang(FRDC),  Li Sun(FRDC),  Jun Sun(FRDC),  

[Date]2017-11-07
[Paper #]CPM2017-86,ICD2017-45,IE2017-71
Implementation and Optimization of Parallel Prefix Adder Using Majority Function

Daiki Matsumoto(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Shinji Kimura(Waseda Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-46,DC2017-52
トリガ条件の異なるハードウェアトロイの設計とSVMを用いた検出

Tomotaka Inoue(Waseda Univ.),  Kento Hasegawa(Waseda Univ.),  Yuki Kobayashi(NEC),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-51,DC2017-57
グリッチ削減のためのパイプライン構造の最適化

Takuya Kojima(Keio Univ.),  Naoki Ando(Keio Univ.),  Hayate Okuhara(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2017-11-07
[Paper #]RECONF2017-41
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