Electronics-Integrated Circuits and Devices(Date:2014/04/10)

Presentation
表紙

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[Date]2014/4/10
[Paper #]
目次

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[Date]2014/4/10
[Paper #]
Hybrid Storage of High-Speed Non-volatile RAM and Flash Memories

Ken Takeuchi,  

[Date]2014/4/10
[Paper #]ICD2014-1
66.3KIOPS-Random-Read 690MB/s-Sequential-Read Universal Flash Storage Device Controller with Unified Memory Extension

Kenichiro YOSHII,  Konosuke WATANABE,  Nobuhiro KONDO,  Kenichi MAEDA,  Toshio FUJISAWA,  Junji WADATSUMI,  Daisuke MIYASHITA,  Shouhei KOUSAI,  Yasuo UNEKAWA,  Shinsuke FUJII,  Takuma AOYAMA,  Takayuki TAMURA,  Atsushi KUNIMATSU,  Yukihito OOWAKI,  

[Date]2014/4/10
[Paper #]ICD2014-2
Requirements for Performance of Non-Volatile Memories in 3D TSV-Integrated Hybrid ReRAM/MLC NAND Solid-State Drive

Kousuke Miyaji,  Hiroki Fujii,  Koh Johguchi,  Kazuhide Higuchi,  Chao Sun,  Ken Takeuchi,  

[Date]2014/4/10
[Paper #]ICD2014-3
Hybrid Storage of ReRAM/TLC NAND Flash with RAID-5/6 for Cloud Data Centers

Hiroki YAMAZAWA,  Tsukasa TOKUTOMI,  Shuhei TANAKAMARU,  Sheyang Ning,  Ken Takeuchi,  

[Date]2014/4/10
[Paper #]ICD2014-4
Design of Exchangeable MLC/TLC Hybrid Storage Array for Big Data

Shogo HACHIYA,  Koh JOHGUCHI,  Kousuke MIYAJI,  Ken TAKEUCHI,  

[Date]2014/4/10
[Paper #]ICD2014-5
Co-design of Application Software and NAND Flash Memory in Solid-State Drive for Database Storage System

Kousuke Miyaji,  Chao Sun,  Ayumi Soga,  Ken Takeuchi,  

[Date]2014/4/10
[Paper #]ICD2014-6
A 1Mb STT-MRAM for Nonvolatile Embedded Memories performing 1.5ns/2.1ns Random Read/Write Cycle Time : Background Write (BGW) Scheme applied to a 6T2MTJ Memory Cell

Takashi OHSAWA,  Hiroki KOIKE,  Sadahiko MIURA,  Keizo KINOSHITA,  Hiroaki HONJO,  Shoji IKEDA,  Takahiro HANYU,  Hideo OHNO,  Tetsuo ENDOH,  

[Date]2014/4/10
[Paper #]ICD2014-7
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine

Shoun MATSUNAGA,  Noboru SAKIMURA,  Ryusuke NEBASHI,  Tadahiko SUGIBAYASHI,  Masanori NATSUI,  Akira MOCHIZUKI,  Tetsuo ENDOH,  Hideo OHNO,  Takahiro HANYU,  

[Date]2014/4/10
[Paper #]ICD2014-8
Perspective of Emerging Memories in Systems and Systems on Emerging Memories

Koji NII,  

[Date]2014/4/10
[Paper #]ICD2014-9
A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier

Yohei UMEKI,  Koji YANAGIDA,  Shusuke YOSHIMOTO,  Shintaro IZUMI,  Masahiko YOSHIMOTO,  Hiroshi Kawaguchi,  Koji TSUNODA,  Toshihiro SUGII,  

[Date]2014/4/10
[Paper #]ICD2014-10
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37V Utilizing Adaptive Back Bias

Y. Yamamoto,  H. Makiyama,  T. Yamashita,  H. Oda,  S. Kamohara,  N. Sugii,  Y. Yamaguchi,  T. Mizutani,  T. Hiramoto,  

[Date]2014/4/10
[Paper #]ICD2014-11
A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current

Toshikazu FUKUDA,  Koji KOHARA,  Toshiaki DOUZAKA,  Yasuhisa TAKEYAMA,  Tsuyoshi MIDORIKAWA,  Kenji HASHIMOTO,  Ichiro WAKIYAMA,  Shinji MIYANO,  Takehiko HOJO,  

[Date]2014/4/10
[Paper #]ICD2014-12
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Keiichi KUSHIDA,  Fumihiko TACHIBANA,  Osamu HIRABAYASHI,  Yasuhisa TAKEYAMA,  Atsushi KAWASUMI,  Azuma SUZUKI,  Yusuke NIKI,  Miyako SHIZUNO,  Shinichi SASAKI,  Tomoaki YABE,  Yasuo UNEKAWA,  

[Date]2014/4/10
[Paper #]ICD2014-13
A 28nm 400MHz 4-Parallel 1.6Gsearch/s 80Mb Ternary CAM

Koji NII,  Teruhiko AMANO,  Naoya WATANABE,  Minoru YAMAWAKI,  Kenji YOSHINAGA,  Mihoko WADA,  Isamu HAYASHI,  

[Date]2014/4/10
[Paper #]ICD2014-14
Multigate FinFET Device and Circuit Technology for 10nm and Beyond

Meishoku MASAHARA,  Kazuhiko ENDO,  Shin-ichi OUCHI,  Takashi MATSUKAWA,  Yongxun Liu,  Shinji MIGITA,  Wataru MIZUBAYASHI,  Yukinori MORITA,  Hiroyuki OTA,  

[Date]2014/4/10
[Paper #]ICD2014-15
Memory-Paper Trend in ISSCC : Analysis of past 10 years and future forecast

Atsushi KAWASUMI,  

[Date]2014/4/10
[Paper #]ICD2014-16
A Power-Gated MPU with 3-μsec Entry/Exit Delay using MTJ-Based Nonvolatile Flip-Flop

Hiroki KOIKE,  Noboru SAKIMURA,  Ryusuke NEBASHI,  Yukihide TSUJI,  Ayuka MORIOKA,  Sadahiko MIURA,  Hiroaki HONJO,  Tadahiko SUGIBAYASHI,  Takashi OHSAWA,  Shoji IKEDA,  Takahiro HANYU,  Hideo OHNO,  Tetsuo ENDOH,  

[Date]2014/4/10
[Paper #]ICD2014-17
DataBase processor (DBP) which can search data ultra-high-speed : The Computing by Memory provides big innovation for information processing

Katsumi INOUE,  Cong-Kha PHAM,  

[Date]2014/4/10
[Paper #]ICD2014-18
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