Electronics-Integrated Circuits and Devices(Date:2013/11/20)

Presentation
表紙

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[Date]2013/11/20
[Paper #]
目次

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[Date]2013/11/20
[Paper #]
Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC

Wataru YOSHIMURA,  Kenichi OHHATA,  

[Date]2013/11/20
[Paper #]CPM2013-108,ICD2013-85
Co-design for reducing power supply noises with On-die PDN Impedance

Ryota KOBAYASHI,  Hiroki OTSUKA,  Genki KUBO,  Sho KIYOSHIGE,  Wataru ICHIMURA,  Masahiro TERASAKI,  Toshio SUDO,  

[Date]2013/11/20
[Paper #]CPM2013-109,ICD2013-86
The design of Via Programmable Analog (VPA) circuit and its performance evaluation compared to programmable analog circuit

Keisuke UEDA,  Ryouhei HORI,  Mitsuru SHIOZAKI,  Toshio KUMAMOTO,  Tomohiro FUJITA,  Takeshi FUJINO,  

[Date]2013/11/20
[Paper #]CPM2013-110,ICD2013-87
Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM

Shintaro Ukai,  Tsunato Nakai,  Toshiki Kitamura,  Takaya Kubota,  Mitsuru Shiozaki,  Takeshi Fujino,  

[Date]2013/11/20
[Paper #]CPM2013-111,ICD2013-88
Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks

Takashi NISHIMURA,  Syuuhei SUGAYA,  Akihiro TAKEUCHI,  Mitsuru SHIOZAKI,  Takeshi FUJINO,  

[Date]2013/11/20
[Paper #]CPM2013-112,ICD2013-89
A Quantizer Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor

Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2013/11/20
[Paper #]CPM2013-113,ICD2013-90
Low Energy Tracking System with Dynamic Frame-Rate Optimization

Serina EGAWA,  Koji INOUE,  

[Date]2013/11/20
[Paper #]CPM2013-114,ICD2013-91
Exploring Microarchitecture for Next Generation Single-Flux-Quantum Processors

Jumpei YOKOTA,  Tomonori TSUHATA,  Koji INOUE,  Masami TANAKA,  

[Date]2013/11/20
[Paper #]CPM2013-115,ICD2013-92
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA

Daisuke SUZUKI,  Masanori NATSUI,  Akira MOCHIZUKI,  Takahiro HANYU,  

[Date]2013/11/20
[Paper #]CPM2013-116,ICD2013-93
Circuit design for 3D-stacking using TSV interconnects

Kenichi Osada,  Futoshi Furuta,  Kenichi Takeda,  

[Date]2013/11/20
[Paper #]VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators

Yasuhiro Take,  Noriyuki Miura,  Hiroki Ishikuro,  Tadahiro Kuroda,  

[Date]2013/11/20
[Paper #]VLD2013-74,CPM2013-118,ICD2013-95,CPSY2013-59,DC2013-40,RECONF2013-42
Cu Wiring Technology for 3D/2.5D Packaging

Motoaki TANI,  Yoshihiro NAKATA,  Tsuyoshi KANKI,  Tomoji NAKAMURA,  

[Date]2013/11/20
[Paper #]VLD2013-75,CPM2013-119,ICD2013-96,CPSY2013-60,DC2013-41,RECONF2013-43
Chip Thinning Technologies for Chip Stacking Packages

Shinya TAKYU,  Tetsuya KUROSAWA,  

[Date]2013/11/20
[Paper #]VLD2013-76,CPM2013-120,ICD2013-97,CPSY2013-61,DC2013-42,RECONF2013-44
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"

Osamu MORI,  

[Date]2013/11/20
[Paper #]VLD2013-86,CPM2013-121,ICD2013-98,CPSY2013-62,DC2013-52,RECONF2013-45
Toward VLSI Reliability Enhancement by Reconfigurable Architecture

Takao ONOYE,  Masanori HASHIMOTO,  Yukio MITSUYAMA,  Dawood ALNAJJAR,  Hiroaki KONOURA,  

[Date]2013/11/20
[Paper #]VLD2013-87,CPM2013-122,ICD2013-99,CPSY2013-63,DC2013-53,RECONF2013-51
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[Date]2013/11/20
[Paper #]
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[Date]2013/11/20
[Paper #]
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[Date]2013/11/20
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