Electronics-Integrated Circuits and Devices(Date:2012/04/16)

Presentation
表紙

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[Date]2012/4/16
[Paper #]
目次

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[Date]2012/4/16
[Paper #]
正誤表

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[Date]2012/4/16
[Paper #]
A 19nm 112.8mm^2 64Gb Multi-level (2bit/cell) Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface

Noboru Shibata,  Kazushige Kanda,  Toshiki Hisada,  Katsuaki Isobe,  Manabu Sato,  Yuui Shimizu,  Takahiro Shimizu,  Takahiro Sugimoto,  Tomohiro Kobayashi,  Kazuko Inuzuka,  Naoaki Kanagawa,  Yasuyuki Kajitani,  Takeshi Ogawa,  Jiyun Nakai,  Kiyoaki Iwasa,  Masatsugu Kojima,  Toshihiro Suzuki,  Yuya Suzuki,  Shintaro Sakai,  Tomofumi Fujimura,  Yuko Utsunomiya,  Toshifumi Hashimoto,  Makoto Miakashi,  Naoki Kobayashi,  Motoki Inagaki,  Yuuki Matsumoto,  Satoshi Inoue,  Yoshinao Suuki,  Dong He,  Yasuhiko Honda,  Junji Musha,  Michio Nakagawa,  Mitsuaki Honma,  Naofumi Abiko,  Masaru Koyanagi,  Masahiro Yoshihara,  Kazumi Ino,  Mitsuhiro Noguchi,  Teruhiko Kamei,  Yosuke Kato,  Shingo Zaitsu,  Hiroaki Nasu,  Takuya Ariki,  Hardwell Chibvongodze,  Mitsuyuki Watanabe,  Hong Ding,  Naoki Ookuma,  Ryuji Yamashita,  Guirong Liang,  Gertjan Hemink,  Farookh Moogat,  Cuong Trinh,  Masaaki Higashitani,  Tuan Pham,  Kazuhisa Kanazawa,  

[Date]2012/4/16
[Paper #]ICD2012-1
128Gb 3-bit/cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate

Teruhiko Kamei,  Yan Li,  Seungpil Lee,  Ken Oowada,  Hao Nguyen,  Qui Nguyen,  Nima Mokhlesi,  Cynthia Hsu,  Jason Li,  Venky Ramachandra,  Masaaki Higashitani,  Tuan Pham,  Mitsuyuki Watanabe,  Mitsuhiro Honma,  Yoshihisa Watanabe,  Kazumi Ino,  Binh Le,  Byungki Woo,  Khin Htoo,  Tai-Yuan Tseng,  Long Pham,  Kwang-ho Kim,  Yi-Chieh Chen,  Min She,  Jong Yuh,  Alex Chu,  Chen Chen,  Ruchi Puri,  Hung-Szu Lin,  Yi-Fang Chen,  William Mak,  Jonathan Huynh,  Jim Chan,  Daniel Yang,  Grishma Shah,  Pavithra Souriraj,  Dinesh Tadepalli,  Suman Tenugu,  Ray Gao,  Viski Popuri,  Behdad Azarbayjani,  Ravindra Madpur,  James Lan,  Emilio Yero,  Feng Pan,  Patrick Hong,  Jang Yong Kang,  Farookh Moogat,  Yupin Fong,  Raul Cernea,  Sharon Huynh,  Cuong Trinh,  Mehrdad Mofidi,  Ritu Shrivastava,  Khandker Quader,  

[Date]2012/4/16
[Paper #]ICD2012-2
An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput

Akifumi Kawahara,  Ryotaro Azuma,  Yuuichirou Ikeda,  Ken Kawai,  Yoshikazu Katoh,  Yukio Hayakawa,  Kiyotaka Tsuji,  Shinichi Yoneda,  Atsushi Himeno,  Kazuhiko Shimakawa,  Takeshi Takagi,  Takumi Mikawa,  Kunitoshi Aono,  

[Date]2012/4/16
[Paper #]ICD2012-3
Dependable SSD design : The Issue for Enabling High Capacity Storage Device with Semiconductor

Hiroshi Sukegawa,  

[Date]2012/4/16
[Paper #]ICD2012-4
Over-10x-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme(Invited Talk)

Shuhei TANAKAMARU,  Yuki YANAGIHARA,  Ken TAKEUCHI,  

[Date]2012/4/16
[Paper #]ICD2012-5
Thinking of Reconstruction of Japan Semiconductor Indutory in Iwate(Panel Discussion)

Shinji Miyano,  

[Date]2012/4/16
[Paper #]ICD2012-6
Non-contact High-Speed Data Links for Memory Interfaces(Invited Talk)

Hiroki Ishikuro,  Won-Joo Yun,  Shinya Nakano,  Wataru Mizuhara,  Atsutake Kosuge,  Noriyuki Miura,  Tadahiro Kuroda,  

[Date]2012/4/16
[Paper #]ICD2012-7
4-Times Faster Rising V_ (10V), 15% Lower Power V_ (20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives

Teruyoshi HATANAKA,  Ken TAKEUCHI,  

[Date]2012/4/16
[Paper #]ICD2012-8
Design of MTJ-Based Fully-Parallel Nonvolatile TCAM

Shoun MATSUNAGA,  Takahiro HANYU,  

[Date]2012/4/16
[Paper #]ICD2012-9
A Non-Volatile Content Addressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells

Ryusuke NEBASHI,  Noboru SAKIMURA,  Yukihide TSUJI,  Shunsuke FUKAMI,  Hiroaki HONJO,  Shinsaku SAITOH,  Sadahiko MIURA,  Nobuyuki ISHIWATA,  Keizo KINOSHITA,  Takahiro HANYU,  Tetsuo ENDOH,  Naoki KASAI,  Hideo OHNO,  Tadahiko SUGIBAYASHI,  

[Date]2012/4/16
[Paper #]ICD2012-10
Write-/Read- Disturb Issues and Circuit Solutions

Yuichiro ISHII,  Yasumasa TSUKAMOTO,  Koji NII,  Hidehiro FUJIWARA,  Makoto YABUUCHI,  Koji TANAKA,  Shinji TANAKA,  Yasuhisa SHIMAZAKI,  

[Date]2012/4/16
[Paper #]ICD2012-11
57% Faster Read, 31% Lower Read Energy, 256-Times Faster Injection 6T-SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Disturb Fails

Kousuke Miyaji,  Toshikazu Suzuki,  Shinji Miyano,  Ken Takeuchi,  

[Date]2012/4/16
[Paper #]ICD2012-12
0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme

Shinichi Moriwaki,  Atsushi Kawasumi,  Toshikazu Suzuki,  Yasue Yamamoto,  Shinji Miyano,  Hirofumi Shinohara,  Takayasu Sakurai,  

[Date]2012/4/16
[Paper #]ICD2012-13
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

Shusuke YOSHIMOTO,  Masaharu TERADA,  Shunsuke OKUMURA,  Toshikazu SUZUKI,  Shinji MIYANO,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2012/4/16
[Paper #]ICD2012-14
Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs

Akira KOTABE,  Kiyoo ITOH,  Riichiro TAKEMURA,  Ryuta TSUCHIYA,  Masashi HORIGUCHI,  

[Date]2012/4/16
[Paper #]ICD2012-15
Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy

Yohei Umeki,  Shunsuke Okumura,  Yohei Nakata,  Koji Yanagida,  Yuki Kagiyama,  Shunsuke Yoshimoto,  Hiroshi Kawaguchi,  Masahiko Yoshimoto,  

[Date]2012/4/16
[Paper #]ICD2012-16
A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST

Hidehiro Fujiwara,  Makoto Yabuuchi,  Hirofumi Nakano,  Hiroyuki Kawai,  Koji Nii,  Kazutami Arimoto,  

[Date]2012/4/16
[Paper #]ICD2012-17
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