IEICE Technical Committee

Electronics-Integrated Circuits and Devices(Date:2011/12/08)

Presentation

表紙

[Date]2011/12/8
[Paper #]

An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Sang_yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu,

[Date]2011/12/8
[Paper #]ICD2011-100

Challenging of semiconductor capability for comfortable human life : Future engineers, what's the role and skill

Kazutami ARIMOTO,

[Date]2011/12/8
[Paper #]ICD2011-101

Tamper LSI Design Methodology using Physical Unclonable Function

Takeshi FUJINO, Kota FURUHASHI, Mitsuru SHIOZAKI,

[Date]2011/12/8
[Paper #]ICD2011-102

A study of the simulation methodology to analyze DC-DC converter's characteristics in high-speed and precise without using SPICE circuit simulator

Tatsuya FURUKAWA, Yuya HIRANO, Yasuhiro SUGIMOTO,

[Date]2011/12/8
[Paper #]ICD2011-103

The design of TDC and ADPLL circuits considering metastable operations

Yasuyuki SHIMIZU, Giichi SAKEMI, Tsutomu YOSHIMURA, Shuhei IWADE, Hiroshi MAKINO, Yoshio MATSUDA,

[Date]2011/12/8
[Paper #]ICD2011-104

Broadband Low Noise Amplifier Design in Scaled CMOS Technology

Ben Patrick, Takana Kaho, Shoichi Masui,

[Date]2011/12/8
[Paper #]ICD2011-105

Analog Circuit Design in Scaled CMOS Technologies

Ying YANG, Jingbo SHI, Ben PATRICK, Takayuki KONISHI, Takana KAHO, Shoichi MASUI,

[Date]2011/12/8
[Paper #]ICD2011-106

A Implementation Technique of a Multibit Succesive Approximation Register AD Converter

Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi,

[Date]2011/12/8
[Paper #]ICD2011-107

Low-Power High-Speed Rail-to-Rail Voltage Buffer for LCD Drivers

Yousuke TSUKAMOTO, Pham Cong Kha,

[Date]2011/12/8
[Paper #]ICD2011-108

Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits

Yasushi KISHIWADA, Shun UEDA, Yusuke MIYAWAKI, Toshimasa MATSUOKA,

[Date]2011/12/8
[Paper #]ICD2011-109

Simulation and Analysis of the Interference Noise between PLL circuits

Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Syuhei Iwade, Hiroshi Makino, Yoshio Matsuda,

[Date]2011/12/8
[Paper #]ICD2011-110

Comparator for A/D converter using time-to-digital converter

Naoki ISOBE, Toshimasa MATSUOKA, Kenji TANIGUCHI,

[Date]2011/12/8
[Paper #]ICD2011-111

Analysis of the Neural Spike Recording Amplifier with Telescopic OPA

Chisato TAKATSUKI, Takeshi YOSHIDA,

[Date]2011/12/8
[Paper #]ICD2011-112

Efficient Execution of Floating Point Instructions in CRIB

Naoaki OHKUBO, Kenji KISE,

[Date]2011/12/8
[Paper #]ICD2011-113

Sleep Depth Controlling for Run-Time Leakage Power Saving

Seidai TAKEDA, Shinobu MIWA, Hiroshi NAKAMURA,

[Date]2011/12/8
[Paper #]ICD2011-114

A study of a 1.5V operational Cyclic Current-mode ADC utilizing the Pipelined conversion architecture

Masatoshi KAMURO, Masanobu OTA, Yasuhiro SUGIMOTO,

[Date]2011/12/8
[Paper #]ICD2011-115

Endurance enhancement programming method for 50nm resistive random access memory (ReRAM)(Poster Presentation)

Kazuhide HIGUCHI, Kousuke MIYAJI, Koh JOHGUCHI, Ken TAKEUCHI,

[Date]2011/12/8
[Paper #]ICD2011-116

4-Times Faster Rising V_(10V), 15% Lower Power V_(20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives(Poster Presentation)

Teruyoshi HATANAKA, Ken TAKEUCHI,

[Date]2011/12/8
[Paper #]ICD2011-117