Electronics-Integrated Circuits and Devices(Date:2010/11/22)

Presentation
表紙

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[Date]2010/11/22
[Paper #]
目次

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[Date]2010/11/22
[Paper #]
Evaluation of frequency components of power noise in CMOS digital LSI

Kumpei YOSHIKAWA,  Hiroshi MATSUMOTO,  Yuta SASAKI,  Makoto NAGATA,  

[Date]2010/11/22
[Paper #]CPM2010-124,ICD2010-83
Evaluation of on-chip power noise generation and injection in SRAM core

Takuya SAWADA,  Taku TOSHIKAWA,  Tsubasa MASUI,  Makoto NAGATA,  

[Date]2010/11/22
[Paper #]CPM2010-125,ICD2010-84
A Consideration of Substrate Noise Sensitivity of Analog Elements

Satoshi TAKAYA,  Yoji BANDO,  Takashi HASEGAWA,  Toru OHKAWA,  Masaaki SOUDA,  Toshiharu TAKARAMOTO,  Toshio YAMADA,  Shigetaka KUMASHIRO,  Tohru MOGAMI,  Makoto NAGATA,  

[Date]2010/11/22
[Paper #]CPM2010-126,ICD2010-85
Evaluation of Signal-Integrity Improvement Capability of the Segmental Transmission Line : In Its Application to Lines Including Inductances

Hiroki SHIMADA,  Shohei AKITA,  Masami ISHIGURO,  Moritoshi YASUNAGA,  Noriyuki AIBE,  Ikuo YOSHIHARA,  

[Date]2010/11/22
[Paper #]CPM2010-127,ICD2010-86
Problems of on-chip interconnection and optical interconnection

Shin YOKOYAMA,  Yoshiteru AMEMIYA,  

[Date]2010/11/22
[Paper #]CPM2010-128,ICD2010-87
Present Status and Target Issue of LSI-Chip Optical Interconnection

Keishi OHASHI,  Tohru MOGAMI,  

[Date]2010/11/22
[Paper #]CPM2010-129,ICD2010-88
Research Trends and Future Directions for Optical Interconnects Technologies

Toshiki SUGAWARA,  Yasunobu MATSUOKA,  Shin-ichi SAITO,  Naoki MATSUSHIMA,  Shinji TSUJI,  

[Date]2010/11/22
[Paper #]CPM2010-130,ICD2010-89
17 Gb/s VCSEL Driver Using Double-Pulse Asymmetric Emphasis Technique for Optical Interconnection

Takaya Taniguchi,  Kiichi Yamashita,  Kenichi Ohhata,  Norio Chujo,  Toru Yazaki,  

[Date]2010/11/22
[Paper #]CPM2010-131,ICD2010-90
Improvement and Evaluation of via programmable structured ASIC VPEX

Ryouhei Hori,  Tatsuya Kitamori,  Taisuke Ueoka,  Masaya Yosikawa,  Takeshi Fujino,  

[Date]2010/11/22
[Paper #]CPM2010-132,ICD2010-91
An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array

Amarjargal GUNDJALAM,  Minoru WATANABE,  

[Date]2010/11/22
[Paper #]CPM2010-133,ICD2010-92
System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology

Masahiro AOYAGI,  

[Date]2010/11/22
[Paper #]CPM2010-134,ICD2010-93
A wafer-level system integration technology for heterogeneous devices with pseudo-SoC

Hiroshi YAMADA,  Yutaka ONOZUKA,  Atsuko IIDA,  Kazuhiko ITAYA,  Hideyuki FUNAKI,  

[Date]2010/11/22
[Paper #]CPM2010-135,ICD2010-94
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[Date]2010/11/22
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