Electronics-Integrated Circuits and Devices(Date:2010/07/15)

Presentation
表紙

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[Date]2010/7/15
[Paper #]
目次

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[Date]2010/7/15
[Paper #]
On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration

Takushi HASHIDA,  Hiroshi MATSUMOTO,  Makoto NAGATA,  

[Date]2010/7/15
[Paper #]ICD2010-21
Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring

Yuuki ARAGA,  Takushi HASHIDA,  Makoto NAGATA,  

[Date]2010/7/15
[Paper #]ICD2010-22
In-situ Evaluation of V_ and AC Gain of 90nm CMOS Differential Pair Transistors

Yoji BANDO,  Satoshi TAKAYA,  Takashi HASEGAWA,  Toru OHKAWA,  Masaaki SOUDA,  Toshiharu TAKARAMOTO,  Toshio YAMADA,  Shigetaka KUMASHIRO,  Tohru MOGAMI,  Makoto NAGATA,  

[Date]2010/7/15
[Paper #]ICD2010-23
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect

Tetsuya IIZUKA,  Toru NAKURA,  Kunihiro ASADA,  

[Date]2010/7/15
[Paper #]ICD2010-24
Digital Calibration and Correction Methods for CMOS-ADCs

Shiro Dosho,  

[Date]2010/7/15
[Paper #]ICD2010-25
A 10b 50MS/s 820μW SAR ADC with Digital Calibration

Sanroku Tsukamoto,  

[Date]2010/7/15
[Paper #]ICD2010-26
Digitally-Assisted Analog Test Technology : Analog Circuit Test Technology in Nano-CMOS Era

Haruo KOBAYASHI,  Takahiro J. YAMAGUCHI,  

[Date]2010/7/15
[Paper #]ICD2010-27
Technical Trend of Multi-mode Multi-band RF Transceivers

Hisayasu Sato,  

[Date]2010/7/15
[Paper #]ICD2010-28
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter

Tadashi MAEDA,  Takashi TOKAIRIN,  Masaki KITSUNEZUKA,  Mitsuji OKADA,  Muneo FUKAISHI,  

[Date]2010/7/15
[Paper #]ICD2010-29
Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply

Tomochika HARADA,  

[Date]2010/7/15
[Paper #]ICD2010-30
OTA Design Using g_m/I_D Lookup Table Methodology : Design optimization featuring Settling Time analysis

Toru KASHIMURA,  Takayuki KONISHI,  Shoichi MASUI,  

[Date]2010/7/15
[Paper #]ICD2010-31
Considerations of a Common-mode Feedback Circuit in the CMOS Inverter-based Differential Amplifier.

Masayuki UNO,  

[Date]2010/7/15
[Paper #]ICD2010-32
The Design of a Highly Linearized Gm Amplifier by Adopting the Positive Feedback Compensation Scheme and its Application to High-Frequency Filters

Yusuke SHIMOYAMA,  Yasuhiro SUGIMOTO,  

[Date]2010/7/15
[Paper #]ICD2010-33
On-chip background calibration of time-interleaved ADC

Takashi Oshima,  Tomomi Takahashi,  

[Date]2010/7/15
[Paper #]ICD2010-34
User Customizable Logic Paper with 2V Organic CMOS and Ink-Jet Printed Interconnects

Koichi ISHIDA,  Naoki MASUNAGA,  Ryo TAKAHASHI,  Tsuyoshi SEKITANI,  Shigeki SHINO,  Ute ZSCHIESCHANG,  Hagen KLAUK,  Makoto TAKAMIYA,  Takao SOMEYA,  Takayasu SAKURAI,  

[Date]2010/7/15
[Paper #]ICD2010-35
Self-Dithered Digital Delta-Sigma Modulators for Fractional-N Frequency Synthesizers

Zule Xu,  Jun Gyu Lee,  Shoichi Masui,  

[Date]2010/7/15
[Paper #]ICD2010-36
A Study of Simulation Methodologies to Simulate the Buck and Boost DC-DC Converters in High-Speed

Masahiro SUZUKI,  Syoko SUGIMOTO,  Yasuhiro SUGIMOTO,  

[Date]2010/7/15
[Paper #]ICD2010-37
Level Converter Circuit for Low Voltage Digital LSIs

Yuji OSAKI,  Tetsuya HIROSE,  Nobutaka KUROKI,  Masahiro NUMA,  

[Date]2010/7/15
[Paper #]ICD2010-38
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