Electronics-Integrated Circuits and Devices(Date:2008/07/10)

Presentation
表紙

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[Date]2008/7/10
[Paper #]
目次

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[Date]2008/7/10
[Paper #]
Impact of the Different Nature of Interface Defect States on the NBTI and 1/f noise of High-κ/Metal Gate pMOSFETs between (100) and (110) Crystal Orientations

Motoyuki SATO,  Yoshihiro SUGITA,  Takayuki AOYAMA,  Yasuo NARA,  Yuzuru OHJI,  

[Date]2008/7/10
[Paper #]SDM2008-128,ICD2008-38
Drain Current Fluctuation in High-κ Dielectric p-MOSFETs : Effects of Single-Hole Capture/Emission by the Traps in High-κ Dielectric

Shigeki KOBAYASHI,  Masumi SAITOH,  Ken UCHIDA,  

[Date]2008/7/10
[Paper #]SDM2008-129,ICD2008-39
Reduction of Vth Variation Utilizing HfSiOx for 45nm SRAM

Gen TSUTSUI,  Kazuaki TSUNODA,  Nayuta KARIYA,  Yutaka AKIYAMA,  Tomohisa ABE,  Shinya MARUYAMA,  Tadashi FUKASE,  Mieko SUZUKI,  Yasushi YAMAGATA,  Kiyotaka IMAI,  

[Date]2008/7/10
[Paper #]SDM2008-130,ICD2008-40
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Makoto YABUUCHI,  Koji NII,  Yasumasa TSUKAMOTO,  Shigeki OHBAYASHI,  Susumu IMAOKA,  Yoshinobu YAMAGAMI,  Satoshi ISHIKURA,  Toshio TERANO,  Katsuji SATOMI,  Hironori AKAMATSU,  Hirofumi SHINOHARA,  

[Date]2008/7/10
[Paper #]SDM2008-131,ICD2008-41
A small-delay defect detection technique for dependable LSIs

Koichiro NOGUCHI,  Koichi NOSE,  Toshinobu ONO,  Masayuki MIZUNO,  

[Date]2008/7/10
[Paper #]SDM2008-132,ICD2008-42
Progress of compact model for CMOS circuit design : Performance of HiSIM model based on the surface potential model

Tatsuya Ohguro,  Michiko Miura-Mattausch,  

[Date]2008/7/10
[Paper #]SDM2008-133,ICD2008-43
Super Chip Technology to Achieve Ultimate Integration

Mitsumasa KOYANAGI,  Tetsu TANAKA,  

[Date]2008/7/10
[Paper #]SDM2008-134,ICD2008-44
Present Status and Future Trend of Characteristic Variations in Scaled CMOS

T. HIRAMOTO,  K. Takeuchi,  T. Tsunomura,  Arifin T. Putra,  A. Nishida,  S. Kamohara,  

[Date]2008/7/10
[Paper #]SDM2008-135,ICD2008-45
A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100ms Retention

N. Kameshiro,  T. Watanabe,  T. Ishii,  T. Mine,  T. Sano,  H. Ibe,  S. Akiyama,  K. Yanagisawa,  T. Ipposhi,  T. Iwanatsu,  Y. Takahashi,  

[Date]2008/7/10
[Paper #]SDM2008-136,ICD2008-46
New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI

Yu HIROSHIMA,  Shigeyoshi Watanabe,  

[Date]2008/7/10
[Paper #]SDM2008-137,ICD2008-47
Co-design of CNT based devices and circuitry : How can CNT-based circuit overcome Si-CMOS?

Shinobu FUJITA,  

[Date]2008/7/10
[Paper #]SDM2008-138,ICD2008-48
Study of high-speed low-power system LSI for sub-threshold operation

Makoto TSURUKUBO,  Shigeyoshi WATANABE,  

[Date]2008/7/10
[Paper #]SDM2008-139,ICD2008-49
Examination of Low-power system LSI architecture by Real time scheduling

Yoshikazu Sato,  Shigeyoshi Watanabe,  

[Date]2008/7/10
[Paper #]SDM2008-140,ICD2008-50
A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support

Koichi NAKAYAMA,  Ken-ichi KAWASAKI,  Tetsuyoshi SHIOTA,  Atsuki INOUE,  

[Date]2008/7/10
[Paper #]SDM2008-141,ICD2008-51
CMOS-based biomedical photonic devices

Takashi TOKUDA,  Jun OHTA,  

[Date]2008/7/10
[Paper #]SDM2008-142,ICD2008-52
Problems and Prospect of 3D Integration using Wireless and Optical Interconnection Technologies

Atsushi IWATA,  Shin YOKOYAMA,  

[Date]2008/7/10
[Paper #]SDM2008-143,ICD2008-53
RF MEMS for Reconfigurable CMOS Radio

Kazuya MASU,  

[Date]2008/7/10
[Paper #]SDM2008-144,ICD2008-54
Realistic future trend of non-volatile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory : feasibility study of BiCS type FeRAM and MRAM

Shigeyoshi Watanabe,  Koichi Sugano,  Shoto Tamai,  

[Date]2008/7/10
[Paper #]SDM2008-145,ICD2008-55
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