Electronics-Integrated Circuits and Devices(Date:2008/05/06)

Presentation
表紙

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[Date]2008/5/6
[Paper #]
目次

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[Date]2008/5/6
[Paper #]
Branch Target Predictor Utilizing Context Base Value Predictor

Tetsuro HIRASHIMA,  Hajime SHIMADA,  Shinobu MIWA,  Shinji TOMITA,  

[Date]2008/5/6
[Paper #]ICD2008-17
Speculation scheme that continues executing mispredicted instructions

Takanobu KITA,  Ryota SHIOYA,  Eiji IRIE,  Masahiro GOSHIMA,  Shuichi SAKAI,  

[Date]2008/5/6
[Paper #]ICD2008-18
Evaluation of Area-Oriented Register Cache

Ryota SHIOYA,  Hidetsugu IRIE,  Masahiro GOSHIMA,  Shuichi SAKAI,  

[Date]2008/5/6
[Paper #]ICD2008-19
An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping

Kaito Yamada,  Masayoshi Mase,  Jun Shirako,  Keiji Kimura,  Masayuki Ito,  Toshihiro Hattori,  Hiroyuki Mizuno,  Kunio Uchiyama,  Hironori Kasahara,  

[Date]2008/5/6
[Paper #]ICD2008-20
Multi-Core Processor for Computer Systems

Yoshio MIKI,  

[Date]2008/5/6
[Paper #]ICD2008-21
マルチコアとしてのCell Broadband Engine^/SpursEngine^(マイクロアーキテクチャ,集積回路とアーキテクチャの協創~どう繋ぐ?どう使う?マルチコア~)

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[Date]2008/5/6
[Paper #]ICD2008-22
Intel's Vision : The Demand for Many Cores : Tera-Scale Usage Models

Yoshie MUNAKATA,  

[Date]2008/5/6
[Paper #]ICD2008-23
新時代におけるマルチコア戦略(マイクロアーキテクチャ,集積回路とアーキテクチャの協創~どう繋ぐ?どう使う?マルチコア~)

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[Date]2008/5/6
[Paper #]ICD2008-24
A Scalable Multi-core Processor for Mobile Multimedia Applications

Hiroyuki USUI,  Shuou NOMURA,  Fumiyuki YAMANE,  Yukimasa MIYAMOTO,  Chaiyasit KUMTORNKITTIKUL,  Jun TANABE,  Masato UCHIYAMA,  Takashi MIYAMORI,  Yoshiro TSUBOI,  

[Date]2008/5/6
[Paper #]ICD2008-25
Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors

Masami NAKAJIMA,  Koichi ISHIMI,  Naoto OKUMURA,  Norio MASUI,  Osamu YAMAMOTO,  Hiroyuki KONDO,  

[Date]2008/5/6
[Paper #]ICD2008-26
PSI-SIM : Performance Prediction for Peta-Scale Supercomputers with Thousands of Multi-core Processors

Koji INOUE,  Ryutaro SUSUKITA,  Hisashige ANDO,  Shigeru ISHIZUKI,  Hidemi KOMATSU,  Yuichi INADOMI,  Hiroaki HONDA,  Shuji YAMAMURA,  Hidetomo SHIBAMURA,  Yunqing YU,  Mutsumi AOYAGI,  Yasunori KIMURA,  Kazuaki MURAKAMI,  

[Date]2008/5/6
[Paper #]ICD2008-27
Design of a Multi-Context Field Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates

Noriaki IDOBATA,  Shota ISHIHARA,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2008/5/6
[Paper #]ICD2008-28
Architecture of a Stereo Matching VLSI Based on Recursive Computation

Keita TANJI,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2008/5/6
[Paper #]ICD2008-29
Automatic Parallelization of Restricted C Programs using Pointer Analysis

Masayoshi MASE,  Daisuke BABA,  Harumi NAGAYAMA,  Yuta MURATA,  Keiji KIMURA,  Hironori KASAHARA,  

[Date]2008/5/6
[Paper #]ICD2008-30
Performance Balancing : An Efficient Helper-Thread Execution on CMPs

Kenichi IMAZATO,  Naoto FUKUMOTO,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2008/5/6
[Paper #]ICD2008-31
Adaptive Management of Parallelism on Transactional Memories

Susumu TAKEDA,  Keita SHIMASAKI,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2008/5/6
[Paper #]ICD2008-32
A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor

Yu KOJIMA,  Daisuke IKEBUCHI,  Naomi SEKI,  Yohei HASEGAWA,  Hideharu AMANO,  Toshihiro KASHIMA,  Seidai TAKEDA,  Toshiaki SHIRAI,  Mitsutaka NAKATA,  Kimiyoshi USAMI,  Tetsuya SUNATA,  Jun KANAI,  Mitaro NAMIKI,  Masaaki KONDO,  Hiroshi Nakamura,  

[Date]2008/5/6
[Paper #]ICD2008-33
Considering Performance and Area Overhead in DVS System Utilizing Input Variations

YUJI Kunitake,  TOSHINORI Sato,  HIROTO Yasuura,  

[Date]2008/5/6
[Paper #]ICD2008-34
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