Electronics-Integrated Circuits and Devices(Date:2008/02/28)

Presentation
表紙

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[Date]2008/2/28
[Paper #]
目次

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[Date]2008/2/28
[Paper #]
A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration

Tetsuro IKEDA,  Atsushi IWATA,  

[Date]2008/2/28
[Paper #]VLD2007-144,ICD2007-167
A -90dBm Sensitivity 0.13μm CMOS Bluetooth Transceiver Operating in Wide Temperature Range

Kenichi AGAWA,  Hideaki MAJIMA,  Hiroyuki KOBAYASHI,  Masayuki KOIZUMI,  Shinichiro ISHIZUKA,  Takeshi NAGANO,  Makoto ARAI,  Yutaka SHIMIZU,  Go URAKAWA,  

[Date]2008/2/28
[Paper #]VLD2007-145,ICD2007-168
Design and Analysis of on-chip leakage monitor using MTCMOS circuits

Satoshi KOYAMA,  Seidai TAKEDA,  Kimiyoshi USAMI,  

[Date]2008/2/28
[Paper #]VLD2007-146,ICD2007-169
Design and Evaluation of the component circuits for the PLL

Yuko Kitaji,  Masayoshi Tachibana,  

[Date]2008/2/28
[Paper #]VLD2007-147,ICD2007-170
Implementation of LCD Driver by nMOS Dynamic Logic

Takuya Hachida,  Hideki Matsunaka,  Isao Shirakawa,  Shuji Tsukiyama,  Masanori Hashimoto,  

[Date]2008/2/28
[Paper #]VLD2007-148,ICD2007-171
A Study for Implementation of High Speed Circuit Simulator by using FPGA

Taiki HASHIZUME,  Seiji MINOURA,  Masashi MIZUTANI,  Hironobu ISHIZIMA,  Shinichi NISHIZAWA,  Masaya YOSHIKAWA,  Masahiro FUKUI,  

[Date]2008/2/28
[Paper #]VLD2007-149,ICD2007-172
Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders

Masayoshi TACHIBANA,  

[Date]2008/2/28
[Paper #]VLD2007-150,ICD2007-173
A Case Study on MPEG4 Decoder Design with SystemBuilder

Seiya Shibata,  Shinya Honda,  Hiroyuki Tomiyama,  Hiroaki Takada,  

[Date]2008/2/28
[Paper #]VLD2007-151,ICD2007-174
Performance Estimation considering False-paths for System-level Design

Daisuke ANDO,  Takeshi MATSUMOTO,  Tasuku NISHIHARA,  Masahiro FUJITA,  

[Date]2008/2/28
[Paper #]VLD2007-152,ICD2007-175
Superposition Effect Validation of Inductive Coupling Noise Based on Measurement of Interconnect Delay Variation

Yasuhiro OGASAHARA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2008/2/28
[Paper #]VLD2007-153,ICD2007-176
Global Routing Method of Plating Lead for 2-Layer BGA Packages

Naoki SATO,  Yoichi TOMIOKA,  Atsushi TAKAHASHI,  

[Date]2008/2/28
[Paper #]VLD2007-154,ICD2007-177
Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI

Satoshi Hanami,  Shigeyoshi Watanabe,  

[Date]2008/2/28
[Paper #]VLD2007-155,ICD2007-178
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[Date]2008/2/28
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[Date]2008/2/28
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[Date]2008/2/28
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