Electronics-Integrated Circuits and Devices(Date:2008/01/10)

Presentation
表紙

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[Date]2008/1/10
[Paper #]
目次

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[Date]2008/1/10
[Paper #]
Non-Contact 10% Efficient 36mW Power Delivery Using On-Chip Inductor in 0.18-μm CMOS

Yuan Yuxiang,  Yoichi Yoshida,  Tadahiro Kuroda,  

[Date]2008/1/10
[Paper #]CPM2007-128,ICD2007-139
Integrated evaluation of on-chip power supply noise and off-chip electromagnetic noise of digital LSI

Yuki TAKAHASHI,  Kouji ICHIKAWA,  Makoto NAGATA,  

[Date]2008/1/10
[Paper #]CPM2007-129,ICD2007-140
Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector

Toru NAKURA,  Taisuke KAZAMA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2008/1/10
[Paper #]CPM2007-130,ICD2007-141
All Digital Gated Oscillator for Dynamic Supply Noise Measurement

Yasuhiro OGASAHARA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2008/1/10
[Paper #]CPM2007-131,ICD2007-142
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise

Yasumi NAKAMURA,  Makoto TAKAMIYA,  Takayasu SAKURAI,  

[Date]2008/1/10
[Paper #]CPM2007-132,ICD2007-143
LSI and PCB Unified Noise Analysis CAD System

Toshiro Sato,  Hiroyuki Orihara,  Shogo Fujimori,  Masaki Tosaka,  

[Date]2008/1/10
[Paper #]CPM2007-133,ICD2007-144
On-Chip Monitoring Technique and Evaluation of Power-Supply Integrity

Makoto NAGATA,  

[Date]2008/1/10
[Paper #]CPM2007-134,ICD2007-145
Techniques for noise management in the supercomputers SX

Jun Inasaka,  Mikihiro Kajita,  

[Date]2008/1/10
[Paper #]CPM2007-135,ICD2007-146
In-situ measurement of supply-noise maps with millivolt accuracy and nanosecond-order time resolution

Yusuke KANNO,  Yuki KONDOH,  Takahiro IRITA,  Kenji HIROSE,  Ryo MORI,  Yoshihiko YASU,  Shigenobu KOMATSU,  Hiroyuki MIZUNO,  

[Date]2008/1/10
[Paper #]CPM2007-136,ICD2007-147
Arithmetic circuits based on abacus architecture

Shunsuke NAGASAWA,  Shugang WEI,  

[Date]2008/1/10
[Paper #]CPM2007-137,ICD2007-148
A compact RF signal quality measurement macro for RF test and diagnosis

Koichi NOSE,  Masayuki MIZUNO,  

[Date]2008/1/10
[Paper #]CPM2007-138,ICD2007-149
A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board That Simulates an Actual Memory Module

Yutaka UEMATSU,  Hideki OSAKA,  Yoji NISHIO,  Susumu HATANO,  

[Date]2008/1/10
[Paper #]CPM2007-139,ICD2007-150
Survey of Analysing Techniques for On-chip Power Distribution Network

Takashi SATO,  

[Date]2008/1/10
[Paper #]CPM2007-140,ICD2007-151
Stress Analysis on Pseudo-SOC Integration : Reduction of Stress between Chip and Resin

Yutaka ONOZUKA,  Hiroshi YAMADA,  Atsuko IIDA,  Kazuhiko ITAYA,  Hideyuki FUNAKI,  

[Date]2008/1/10
[Paper #]CPM2007-141,ICD2007-152
An Extraction Method of Material Constants by Transmission Line Measurements

Hiroshi TOYAO,  Yoshiaki WAKABAYASHI,  

[Date]2008/1/10
[Paper #]CPM2007-142,ICD2007-153
A Package-on-Package using Coreless Substrate with Excellent Power Integrity : The electrical characteristics of MLTS and the novel PoP structure

Kentaro Mori,  Jun Sakai,  Katsumi Kikuchi,  Shinji Watanabe,  Tomoo Murakami,  Shintaro Yamamichi,  

[Date]2008/1/10
[Paper #]CPM2007-143,ICD2007-154
Assessment Test for Solder Joint Reliability in Mobile Products

Masazumi AMAGAI,  Hiroyuki SANO,  

[Date]2008/1/10
[Paper #]CPM2007-144,ICD2007-155
Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength

Shinya TAKYU,  Tetsuya KUROSAWA,  Noriko SHIMIZU,  Susumu HARADA,  

[Date]2008/1/10
[Paper #]CPM2007-145,ICD2007-156
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